Waveform Generation Fundamental part of signal processing is the - - PowerPoint PPT Presentation

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Waveform Generation Fundamental part of signal processing is the - - PowerPoint PPT Presentation

Aug 25, 2022 225 likes •498 views

Waveform Generation Fundamental part of signal processing is the signal. Within the context of hardware implementations of signal processing this signal may arise from: A local waverform/signal generator. Continuous stream from a

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SLIDE 1

Waveform Generation

  • Fundamental part of signal processing is

the signal.

  • Within the context of hardware

implementations of signal processing this signal may arise from:

  • A local waverform/signal generator.
  • Continuous stream from a processor bus.
  • Samples from a Analog-to-Digital Coverters

(ADCs from the outside world).

  • We also need to get these signals into the
  • utside world:
  • Digital-to-analog Converters (DACs)
  • Over the next few lectures we will

investigate these topics.

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SLIDE 2

Waveform Generation

  • Some common types of waveform signal

generators:

  • Ramp Generator.
  • Arbitrary Waveform Generator (AWG)
  • Period Signal Generator - Pulse Train
  • Sinusoidal Signals- Direct Digital

Synthesizer (DDS)

  • (Pseudo) Random Number Generator (RNG)
  • Communication signals & Modulation
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SLIDE 3

Time Base

  • Common to all these types of signals

and waveform generators we need some type of time base (sample base) “n”, which will consist of:

  • Sample duration (Δt = 1/fSMP)
  • Used to relate the signal to the outside world.
  • Sample count (n)
  • The sample base itself.
  • Count Limit (N)
  • Since hardware numbers are confined to a finite

width.

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SLIDE 4

Implementation

  • A sample base can be implemented with a

simple counter.

N-1 1 z-1 = n n_next wrap sum module counter #( parameter WIDTH = W, parameter LIMIT = N) ( input wire clock,

  • utput reg

[WIDTH-1:0] n = 0,

  • utput wire wrap);

wire [WIDTH-1:0] n_next; wire [WIDTH-1:0] sum; assign wrap = (n == (LIMIT-1)); assign sum = n + 1; assign n_next = wrap ? 0 : sum; always@(posedge clock) n <= n_next; endmodule z-1 1 The “clock” is not explicitly shown in the block diagram? Where is it?

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SLIDE 5

Simulation

`timescale 1ns/1ps module ex1_tb; localparam WIDTH=8; localparam N=24; reg clock; wire [WIDTH-1:0] n; wire wrap; counter #( .WIDTH(WIDTH), .LIMIT(N)) dut ( .clock(clock), .n(n), .wrap(wrap)); always begin clock <= 1'b0; #5; clock <= 1'b1; #5; end endmodule Not only do we have a sample base to generate other waveforms, we also have a signal – ramp.

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SLIDE 6

Configurable Logic Block

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SLIDE 7

Implementation

  • A slight modification.

N-1 1 z-1 = n n_next wrap sum module counter #( parameter WIDTH = W, parameter LIMIT = N) ( input wire clock, input wire reset, input wire enable,

  • utput reg

[WIDTH-1:0] n = 0,

  • utput wire wrap);

wire [WIDTH-1:0] n_next; wire [WIDTH-1:0] sum; assign wrap = (n == (LIMIT-1)); assign sum = n + 1; assign n_next = wrap ? 0 : sum; always@(posedge clock) begin if (reset) n <= 0; else if (enable) n <= n_next; end endmodule z-1 1

  • The “clock” is not explicitly shown

in the block diagram?

  • Where is it?
  • Similar for reset & enable.
  • These already exist in the hardware.
  • Just need to hook them up.

clock reset enable

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SLIDE 8

Simulation

... wire [2:0] n0; wire [4:0] n1; wire wrap0; wire wrap1; counter #( .WIDTH(3), .LIMIT(6)) dut0 ( .clock(clock), .reset(1’b0), .enable(1’b1), .n(n0), .wrap(wrap0)); counter #( .WIDTH(5), .LIMIT(24)) dut1 ( .clock(clock), .reset(1’b0), .enable(wrap0); .n(n1), .wrap(wrap1)); ... time expansion for n1; What about time compression;

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SLIDE 9

Implementation

  • A slight modification.

LIMIT-STEP 1 z-1 >= n n_next wrap sum module counter #( parameter WIDTH = W, parameter LIMIT = N, parameter STEP = D) ( input wire clock, input wire reset, input wire enable,

  • utput reg

[WIDTH-1:0] n = 0,

  • utput wire wrap);

wire [WIDTH-1:0] n_next; wire [WIDTH-1:0] sum; wire [WIDTH-1:0] diff; assign wrap = (n >= (LIMIT-STEP)); assign sum = n + STEP; assign diff = n-(LIMIT-STEP); assign n_next = wrap ? diff : sum; always@(posedge clock) begin if (reset) n <= 0; else if (enable) n <= n_next; end endmodule z-1 STEP clock reset enable

  • subtraction

diff

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SLIDE 10

Simulation

... wire [7:0] n0; wire wrap0; counter #( .WIDTH(8), .LIMIT(32), .STEP(4)) dut0 ( .clock(clock), .reset(1’b0), .enable(1’b1), .n(n0), .wrap(wrap0)); ... Count by 4’s. What about fractional?

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SLIDE 11

Simulation

... wire [2:0] n0; wire [4:0] n1; wire wrap0; wire wrap1; counter #( .WIDTH(3), .LIMIT(5), .STEP(3)) dut0 ( .clock(clock), .reset(1’b0), .enable(1’b1), .n(n0), .wrap(wrap0)); counter #( .WIDTH(5), .LIMIT(24), .STEP(1)) dut1 ( .clock(clock), .reset(1’b0), .enable(wrap0); .n(n1), .wrap(wrap1)); ... wrap0 is high 3/5th of the time.

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SLIDE 12

Pulse Train

Counter n wrap LIMIT(200) STEP(1) clock reset enable < WIDTH DUTY CYCLE = WIDTH/LIMIT *not* Clock, reset, enable are assumed to be connected to a clock, reset=0, enable=1.

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SLIDE 13

The Arbitrary Waveform Generator

Counter n wrap LIMIT(DEPTH) STEP(1) clock reset enable Memory Addr Data DEPTH() WIDTH() ROM_FILENAME() clock reset enable address

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SLIDE 14

Verilog Memory

  • Verilog memory can be inferred from the

register array definition.

module waveform_rom #( parameter DATA_WIDTH = XX, parameter ROM_DEPTH = XX, parameter ADDR_WIDTH = XX, parameter ROM_FILENAME = “wave.mem”) ( input wire clock, input wire reset, input wire enable, input wire [ADDR_WIDTH-1:0] addr,

  • utput reg

[DATA_WIDTH-1:0] do = 0); reg [DATA_WIDTH-1:0] rom [ROM_DEPTH-1:0]; initial $readmemh(ROM_FILENAME,rom); always@(posedge clock) begin if (reset) do <= 0; else if (enable) do <= rom[addr]; end endmodule If the rom register variable is used incorrectly, the build tools may not be able to make use of the BLOCK RAM available within the PL.

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SLIDE 15

Simulation

... counter #( .WIDTH(12), .LIMIT(4096), .STEP(1)) dut0 ( .clock(clock), .reset(1'b0), .enable(1'b1), .n(addr), .wrap(wrap0)); waveform_rom #( .DATA_WIDTH(12), .ROM_DEPTH(4096), .ADDR_WIDTH(12)) wfm0 ( .clock(clock), .reset(1'b0), .enable(1'b1), .addr(addr), .do(do)); always begin clock <= 1'b0; #5; clock <= 1'b1; #5; end ...

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SLIDE 16

The Arbitrary Waveform Generator

Counter n wrap LIMIT(DEPTH) STEP(1) clock reset enable Memory Addr Data DEPTH() WIDTH() ROM_FILENAME() clock reset enable Stop after one pulse, Trigger to initiate. Trigger address

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SLIDE 17

The Arbitrary Waveform Generator

Trigger Counter n wrap LIMIT(DEPTH) STEP(S) clock reset enable Memory Addr Data DEPTH() WIDTH() ROM_FILENAME() clock reset enable Counter n wrap LIMIT(L) STEP(1) clock reset enable

  • Stop after one pulse, Trigger to initiate.
  • Time Scale of S/L.
  • For a specific ratio it typically is best

to find the lowest denominator.

  • For example S/L of 2/3 is better than 4/6.

rate address

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SLIDE 18

The Arbitrary Waveform Generator

Trigger Counter n wrap LIMIT(DEPTH) STEP(S) clock reset enable Memory Addr Data DEPTH() WIDTH() ROM_FILENAME() clock reset enable Counter n wrap LIMIT(L) STEP(1) clock reset enable

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SLIDE 19

... counter #( .WIDTH(12), .LIMIT(4096), .STEP(1)) dut0 ( .clock(clock), .reset(1'b0), .enable(1'b1), .n(addr), .wrap(wrap0)); waveform_rom #( .DATA_WIDTH(12), .ROM_DEPTH(4096), .ADDR_WIDTH(12)) wfm0 ( .clock(clock), .reset(1'b0), .enable(1'b1), .addr(addr), .do(do)); always begin clock <= 1'b0; #5; clock <= 1'b1; #5; end ...

Back a few slides

  • What if the waveform is one cycle of a

sinusoid?

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SLIDE 20

... counter #( .WIDTH(12), .LIMIT(4096), .STEP(1)) dut0 ( .clock(clock), .reset(1'b0), .enable(1'b1), .n(addr), .wrap(wrap0)); waveform_rom #( .DATA_WIDTH(12), .ROM_DEPTH(4096), .ADDR_WIDTH(12)) wfm0 ( .clock(clock), .reset(1'b0), .enable(1'b1), .addr(addr), .do(do)); always begin clock <= 1'b0; #5; clock <= 1'b1; #5; end ...

Back a few slides

  • What if the waveform is one cycle of a

sinusoid?

Direct Digital Synthesizer (DDS)

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SLIDE 21

DDS

  • Clock frequency is 100MHz
  • ROM Depth is 64 and contains 1 cycle.
  • What is the signal frequency.
  • Period =
  • Frequency = 1/Period =
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SLIDE 22

DDS

Counter n wrap LIMIT(D) STEP(S) clock reset enable Memory Addr Data “single cycle” DEPTH(D) WIDTH() ROM_FILENAME() clock reset enable Counter n wrap LIMIT(L) STEP(1) clock reset enable Variables

  • F: Clock frequency
  • D: number of points in the sine single cycle rom file.
  • S: step size of address counter
  • L: limit of the rate counter

Frequency Fout = address rate

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SLIDE 23

DDS

Memory Addr Data “single cycle” DEPTH(D) WIDTH() ROM_FILENAME() clock reset enable Variables

  • F: Clock frequency
  • D: number of points in the sine single cycle rom file.
  • S: step size of address counter
  • L: limit of the rate counter

Frequency Fout = (F/D)*(S/L) address rate Counter limit n step wrap WIDTH() clock reset enable Counter limit n step wrap WIDTH() clock reset enable 1 D L S

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SLIDE 24

DDS

Memory Addr Data “single cycle” DEPTH(D) WIDTH() ROM_FILENAME() clock reset enable What does this do? address rate Counter limit n step wrap WIDTH() clock reset enable Counter limit n step wrap WIDTH() clock reset enable 1 D L Counter limit n step wrap WIDTH() clock reset enable K D

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SLIDE 25

The Rate Counter?

Memory Addr Data “single cycle” DEPTH(D) WIDTH() ROM_FILENAME() clock reset enable address rate Counter limit n step wrap WIDTH() clock reset enable Counter limit n step wrap WIDTH() clock reset enable 1 D L Counter limit n step wrap WIDTH() clock reset enable K D The Rate Counter is acting as a clock divider, effectively reducing the update rate of all the downstream components. Here it is done correctly, but do not fall in the following trap.

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SLIDE 26

Divide clock by 4.

Clock Div Counter limit n[1] step wrap WIDTH(2) clock reset enable 1 4 Here it is done incorrectly. Counter limit n step wrap WIDTH() clock reset enable Clock Div Counter limit n[1] step wrap WIDTH(2) clock reset enable 1 4 Counter limit n step wrap WIDTH() clock reset enable Here it is done correctly.