[PPT] - MOS: Device Operation & Large Signal Model Lecture notes: Sec. PowerPoint Presentation

SLIDE 1

MOS: Device Operation & Large Signal Model

Lecture notes: Sec. 4 Sedra & Smith (6th Ed): Sec. 5.1-5.3 Sedra & Smith (5th Ed): Sec. 4.1-4.3

F. Najmabadi, ECE65, Winter 2012

SLIDE 2

Operational Basis of a Field-Effect Transistor (1)

F. Najmabadi, ECE65, Winter 2012

P-type semiconductor Insulator Metal Dopent ions Holes (majority carries)

Consider the hypothetical semiconductor below: (constructed similar to a parallel plate capacitor)

Electrical contact

SLIDE 3

Operational Basis of a Field-Effect Transistor (2)

If we apply a voltage v1 between electrodes, a

charge Q = C v1 will appear on each capacitor plate.

The electric field is strongest at the interface with the

insulator and charge likes to accumulate there.

Holes are pushed away from the insulator

interface forming a “depletion region”.

Depth of depletion region increases with v1.
F. Najmabadi, ECE65, Winter 2012

Depletion Region (no majority carrier)

If we increase v1 above a threshold value (Vt),

the electric field is strong enough to “pull” free electrons to the insulator interface. As the holes are repelled in this region, a “channel” is formed which contains electrons in the conduction band (“inversion layer”).

Inversion layer is a “virtual” n-type material.

Depletion Region (no majority carrier)

Inversion layer (“channel”)

SLIDE 4

Operational Basis of a Field-Effect Transistor (3)

F. Najmabadi, ECE65, Winter 2012

With inversion layer (v1 > Vt):

A current will flow in the channel
Current will be proportional to electron

charge in the channel or (v1 − Vt )

Magnitude of Current i2 is controlled by

voltage v1 (a Transistor!)

We apply a voltage across the p-type semiconductor:

(Assume current flows only in the n-type material, ignore current flowing in the p-type semiconductor)

No inversion layer (v1 < Vt):

No current will flow

SLIDE 5

Operational Basis of a Field-Effect Transistor (4)

F. Najmabadi, ECE65, Winter 2012
We need to eliminate currents flowing in the p-type, i.e.,

current flows only in the “channel” which is a virtual n-type.

SLIDE 6

Channel width (L) is the smallest feature on the chip surface

F. Najmabadi, ECE65, Winter 2012

MOSFET implementation on a chip MOSFET “cartoons” for deriving MOSFET characteristics MOSFET (or MOS): Metal-oxide field effect transistor NMOS: n-channel enhancement MOS

SLIDE 7

NMOS i-v Characteristics (1)

F. Najmabadi, ECE65, Winter 2012
To ensure that body-source and body-drain junctions are reversed bias, we

assume that Body and Source are connected to each other and vDS ≥ 0.

We will re-examine this assumption later
Without a channel, no current flows (“Cut-off”).
For vGS > Vtn, a channel is formed. The total

charge in the channel is ) SiO (for F/m 10 45 . 3 9 . 3 insulator

f

y permitivit : insulator

f

Thickness : area unit per e Capacitanc :

2 11 −

× = = = = = = ε ε ε ε

x
x
x
x
x
x
x

tn GS

x

t t C L W C C )

V

WL (v C CV |Q|

SLIDE 8

NMOS i-v Characteristics (2)

F. Najmabadi, ECE65, Winter 2012
vGS > Vtn : a channel is formed!
Apply a “small” voltage, vDS between drain & source.
A current flow due to the “drift” of electrons in the

n-channel:

DS OV

x

n D DS n t GS

x

n D

v V L W C i v V v L W C i ) (

,

µ µ = − = MOS acts as a resistance with its conductivity controlled by VOV (or vGS). V L W C g v g i

OV

x

n DS DS DS D

with µ = = Overdrive Voltage:

tn GS OV

V v V − =

SLIDE 9

NMOS i-v Characteristics (3)

F. Najmabadi, ECE65, Winter 2012
When vDS is increased the channel becomes narrower

near the drain (local depth of the channel depends on the difference between VOV and local voltage).

Triode Mode

[ ]

2

5 .

DS DS OV

x

n D

v v V L W C i − = µ

When vDS is increased further such that vDS = VOV ,

the channel depth becomes zero at the drain (Channel “pinched off”).

When vDS is increased further, vDS > VOV , the

location of channel pinch-off remains close to the drain and iD remains approximately constant.

Saturation Mode

2

5 .

OV

x

n D

V L W C i µ =

SLIDE 10

NMOS i-v Characteristics (4)

F. Najmabadi, ECE65, Winter 2012

For a given vGS (or VOV)

SLIDE 11

NMOS i-v Characteristics Plot (1)

F. Najmabadi, ECE65, Winter 2012
NMOS i-v characteristics is a surface

* Plot for Vt,n = 1 V and µnCox (W/L) = 2.0 mA/V2

) , (

DS GS D

v v f i =

SLIDE 12

NMOS i-v Characteristics Plot (2)

F. Najmabadi, ECE65, Winter 2012

Looking at surface with vGS axis pointing out of the paper* *Note: surface is truncated (i.e., vGS < 5 V)

SLIDE 13

NMOS i-v Characteristics Plots

F. Najmabadi, ECE65, Winter 2012

SLIDE 14

Channel-Width Modulation

F. Najmabadi, ECE65, Winter 2012
The expression we derived for saturation region

assumed that the pinch-off point remains at the drain and thus iD remains constant.

In reality, the pinch-off point moves “slightly” away

from the drain: Channel-width Modulation

( )

A DS OV

x

n D

V v V L W C i / 1 1 5 .

2

= + = λ λ µ

SLIDE 15

Body Effect

Recall that Drain-Body and Source-Body diodes should be reversed biased.
We assumed that Source is connected to the body (vSB = 0) and vDS = vDB > 0
In a chip (same body for all NMOS), it is impossible to connect all sources

to the body (all NMOS sources are connected together.

Thus, the body (for NMOS) is connected to the largest negative voltage

(negative terminal of the power supply).

Doing so, changes the threshold voltage (called “Body Effect”)
F. Najmabadi, ECE65, Winter 2012

( )

| 2 | | 2 |

, F SB F tn tn

V V V φ φ γ − + + =

In this course we will ignore body effect as well as other second-
rder effects such as velocity saturation.

SLIDE 16

p-channel Enhancement MOS (PMOS)

F. Najmabadi, ECE65, Winter 2012
A PMOS can be constructed analogous to an NMOS: (n-type body),

heavily doped p-type source and drain.

A virtual “p-type” channel is formed in a P-MOS (holes are carriers in

the channel) by applying a negative vGS.

i-v characteristic equations of a PMOS is similar to the NMOS with the

exception:

Voltages are negative (we switch the terminals to have positive voltages:

use vSG instead of vGS ).

Use mobility of holes, µp , instead of µn in the expression for iD

SLIDE 17

MOS Circuit symbols and conventions

F. Najmabadi, ECE65, Winter 2012

PMOS NMOS

SLIDE 18

MOS i-v Characteristics Equations: iD (vGS , vDS ) & iG = 0

F. Najmabadi, ECE65, Winter 2012

*Note: S&S defines |VOV |= vSG – |Vt,p| and uses |VOV |in the PMOS formulas.

PMOS (VOV = vSG – |Vtp|, λ = 1 / |VA| )*

[ ] [ ]

SD OV

x

p D OV SD OV SD SD OV

x

p D OV SD OV D OV

v V L W C i V v V v v V L W C i V v V i V λ µ µ + = ≥ ≥ − = ≤ ≥ = ≤ 1 5 . and : Saturation 2 5 . and : Triode : Off

Cut

2 2

NMOS (VOV = vGS – Vtn, λ = 1 / VA)

[ ]

DS OV

x

n D OV DS OV DS DS OV

x

n D OV DS OV D OV

v V L W C i V v V v v V L W C i V v V i V λ µ µ + = ≥ ≥ − = ≤ ≥ = ≤ 1 5 . and : Saturation 2 5 . and : Triode : Off

Cut

2 2

SLIDE 19

MOS operation is “Conceptually” similar to a BJT -- iD & vDS are controlled by vGS

F. Najmabadi, ECE65, Winter 2012

Controller part: Circuit connected to GS sets vGS (or VOV ) Controlled part: iD & vDS are set by transistor state (&

utside circuit)
A similar solution method to BJT:
Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve

with the corresponding MOS equation and validate the assumption.

MOS circuits are simpler to solve because iG = 0 !
However, we get a quadratic equation to solve if MOS in triode (check MOS

in saturation first!)

SLIDE 20

F. Najmabadi, ECE65, Winter 2012

Example 1: In the circuit below, RD = 1 k, and VDD = 12 V. Compute vo for vi = 0, 6, and 12 V. (µnCox (W/L) = 0.5 mA/V2 , Vt = 2 V, and λ = 0 )

DS D DS D D DD GS i

v i v i R V v v + = + = = = 10 12 : KVL

DS

: KVL

GS

3

V 12 10 12 : KVL

DS
ff
Cut

V 2 : KVL

GS

3

= = → + × = = → → = < = =

DS

DS

D t GS i

v v v i V v v correct Assumption V 4 V . 8 V . 8 10 4 10 12 : KVL

DS

mA . 4 4 10 5 . 5 . 5 . V 4 : Saturation Assume

3 3 2 3 2

→ = > = = = → + × × = = × × × = = = ≥

− − OV DS DS

DS

OV

x

n D OV DS

V v v v v V L W C i V v µ

Part 1: vi = 0

V 4

ff
Cut

in Not V 2 6 : KVL GS = − = → = > = = −

t GS OV t GS i

V v V V v v

Part 2: vi = 6 V

DS

v v =

SLIDE 21

Example 1: In the circuit below, RD = 1 k, and VDD = 12 V. Compute vo for vi = 0, 6, and 12 V. (µnCox (W/L) = 0.5 mA/V2 , Vt = 2 V, and λ = 0 )

F. Najmabadi, ECE65, Winter 2012

DS D DS D D DD GS i

v i v i R V v v + = + = = = 10 12 : KVL

DS

: KVL

GS

3

incorrect Assumption V 10 V 13 V . 13 10 . 25 10 12 : KVL

DS

mA . 25 10 10 5 . 5 . 5 . V 10 : Saturation Assume

3 3 2 3 2

→ = > − = − = → + × × = = × × × = = = ≥

− − OV DS DS DS OV

x

n D OV DS

V v v v V L W C i V v µ V 10

ff
Cut

in Not V 2 12 : KVL

GS

= − = → = > = =

t GS OV t GS i

V v V V v v

Part 3: vi = 12 V

DS

v v =

SLIDE 22

Example 1: In the circuit below, RD = 1 k, and VDD = 12 V. Compute vo for vi = 0, 6, and 12 V. (µnCox (W/L) = 0.5 mA/V2 , Vt = 2 V, and λ = 0 )

F. Najmabadi, ECE65, Winter 2012

DS D DS D D DD GS i

v i v i R V v v + = + = = = 10 12 : KVL

DS

: KVL

GS

3

[ ]

48 24 ] 20 [ 10 5 . 5 . 10 12 10 12 : KVL

DS

2 5 . V 10 : Triode Assume

2 2 3

3

3 2

= + − + − × × × × = + × = − = = <

DS DS DS DS DS DS D DS DS OV

x

n D OV DS

v v v v v v i v v V L W C i V v µ V 10 = − =

t GS OV

V v V

Part 3 (cont’d): vi = 12 V

DS

v v = mA 8 . 9 10 12 V 10 V 2 . 2 ) (incorrect V 8 . 21

3

= → + × = = < = = = =

D DS D OV DS

DS
i

v i V v v v v

SLIDE 23

NMOS Transfer Function (1)

F. Najmabadi, ECE65, Winter 2012

) , (

DS GS D DS D D DD i GS

v v f i v i R V v v = + = =

For vGS < Vt , NMOS is in cutoff: iD = 0

DD D D DD DS

V

i R V v v = − = =

vi can be applied directly to MOS There is no need for a RG .

SLIDE 24

NMOS Transfer Function (1)

F. Najmabadi, ECE65, Winter 2012

) , (

DS GS D DS D D DD i GS

v v f i v i R V v v = + = =

For vGS < Vt , NMOS is in cutoff: iD = 0

DD D D DD DS

V

i R V v v = − = =

vi can be applied directly to MOS There is no need for a RG .

SLIDE 25

NMOS Transfer Function (2)

F. Najmabadi, ECE65, Winter 2012
To the right of point A, vGS >Vt,

and NMOS is ON.

Just to the right of point A:
VOV = vGS − Vt is small. So iD is

also small and vDS is close to VDD .

Thus, vDS > VOV and NMOS is in

saturation.

2 2 2

5 . 5 .

OV D OV

x

n DD DS OV

x

n D

V R V L W C V v V L W C i       − = = µ µ

SLIDE 26

NMOS Transfer Function (3)

F. Najmabadi, ECE65, Winter 2012
As vGS increase:
VOV = vGS − Vt becomes larger;
vDS becomes smaller.
At point B, vDS = VOV = vGS − Vt
To the right of point B, vDS <

VOV = vGS − Vt and NMOS enters triode.

Point B is called the “Edge of

Saturation”

Exercise: Use NMOS i-v characteristics (and DS-KVL) to find VGS|B and VDS|B

SLIDE 27

Graphical analysis of NMOS Transfer Function

F. Najmabadi, ECE65, Winter 2012
NMOS iD (vGS , vDS ) is a surface in the

3-D (iD , vGS , vDS ) space.

DS-KVL is a plane in this space.
Intersection of KVL plane with the iv

characteristic surface is a line.

NMOS operating point is on this line

(depending on the value of vGS.)

If we look from the side (with vGS axis

pointing into the paper, we see contour plots of NMOS iD (vGS , vDS )

SLIDE 28

Graphical analysis of NMOS Transfer Function

Every point on the load line

corresponds to a specific vGS value.

As vGS increases, NMOS moves

“up” the load line. A B C We see the transfer function if we look this way!

F. Najmabadi, ECE65, Winter 2012

SLIDE 29

NMOS Functional circuits

Similar to a BJTSin the active mode,

NMOS behaves rather “linearly” in the saturation region (we discuss NMOS amplifiers later)

Transition from cut-off to triode can

be used to build NMOS switch circuits.

Voltage at point C (see graph)

depends on NMOS parameters and the circuit (in BJT vo = Vsat)!

We can also built NMOS logic gate

similar to a RTL. But there is a much better gate based on CMOS technology!

F. Najmabadi, ECE65, Winter 2012

SLIDE 30

Complementary MOS (CMOS) is based on NMOS/PMOS pairs

Maximum signal swing: Low State: 0, High State: VDD
Independent of MOS device parameters!
Wide noise margin.
Zero “static” power dissipation (iD = 0 in each state).
Higher speed compare to a “RTL-type” NMOS inverter
F. Najmabadi, ECE65, Winter 2012

NMOS Inverter

Replace RD with a PMOS
“Effective” RD seen by Q1 is

controlled by vi :

“Infinite” RD when Q1 is ON
“Very small” RD when Q1 is OFF

CMOS Inverter

SLIDE 31

Analysis of CMOS Inverter (1)

F. Najmabadi, ECE65, Winter 2012

2 1 2 1 1 2 2 2 1

: KVL 2 & DS1 : KVL GS2 : KVL GS1

SD DD DS

D

D DS SD DD i DD SG i SG DD i GS

v V v v i i v v V v V v v v V v v − = = = + = − − = → + = − = −

Case 1: vi = 0

ON Q2 OFF Q1

2 1 1

→ > = − = ↓ = → → < = = | |V V v V v i V v v

tp DD i DD SG D tn i GS

ON Q2 OFF Q1

2 2 1 1

= → > = − = ↓ = → → < = =

D tp DD i DD SG D tn i GS

i | |V V v V v i V v v KCL

?

SLIDE 32

A MOS in ON and iD = 0

nly if MOS is in triode and vDs = 0
F. Najmabadi, ECE65, Winter 2012

MOS ON: VOV > 0

MOS in saturation: incorrect!
MOS in triode:

5 .

2

= → = =

OV OV

x

n D

V V L W C i µ

[ ]

2 5 .

2

= → = − =

DS DS DS OV

x

n D

v v v V L W C i µ

When is iD = 0 ?

MOS is OFF (VOV < 0)
No channel is formed, no iD can flow
MOS is ON (VOV > 0)
A channel is formed, and iD can flow

but iD = 0 because no voltage is applied to drive iD !

SLIDE 33

Analysis of CMOS Inverter (2)

F. Najmabadi, ECE65, Winter 2012

2 1 2 1 1 2 2 2 1

: KVL 2 & DS1 : KVL GS2 : KVL GS1

SD DD DS

D

D DS SD DD i DD SG i SG DD i GS

v V v v i i v v V v V v v v V v v − = = = + = − − = → + = − = −

Case 1: vi = 0

& Triode in Q2 ON Q2 OFF Q1

2 2 2 1 1 1

= → = → = − = ↑ ↓ = = → → < = =

SD D DD i DD SG DD DS D tn i GS

v i V v V v V v i V v v

For vi = 0, vo = vDS1 = VDD (iD1 = 0, iD2 = 0 )
Gate remains in this state as long as vi < Vtn (Q1 OFF)

ON Q2 OFF Q1

2 2 1 1

= → = − = ↓ = → → < = =

D DD i DD SG D tn i GS

i V v V v i V v v

SLIDE 34

OFF Q2 | | ON Q1

2 2 1

= → → < = − = ↑ → > = =

D tp i DD SG tn DD i GS

i V v V v V V v v

Analysis of CMOS Inverter (3)

F. Najmabadi, ECE65, Winter 2012

Case 2: vi = VDD

2 1 2 1 1 2 2 2 1

: KVL 2 & DS1 : KVL GS2 : KVL GS1

SD DD DS

D

D DS SD DD i DD SG i SG DD i GS

v V v v i i v v V v V v v v V v v − = = = + = − − = → + = − = − OFF Q2 | | & Triode in Q1 ON Q1

2 2 2 1 1 1 DD SD D tp i DD SG DS D tn DD i GS

V v i V v V v v i V V v v = = → → < = − = ↓ ↑ = → = → > = =

For vi = VDD, vo = vDS1 = 0 (iD1 = 0, iD2 = 0 )
Gate remains in this state as long as vi > VDD − |Vtp| (Q2 OFF)

OFF Q2 | | ON Q1

2 2 1 1

= → → < = − = ↑ = → > = =

D tp i DD SG D tn DD i GS

i V v V v i V V v v

SLIDE 35

Transfer function of a CMOS inverter

Transfer function is “symmetric” for matched transistors:

Vtn=|Vtp| & µn (W/L)n = µp (W/L)p

During transition from one state to another, iD > 0
F. Najmabadi, ECE65, Winter 2012

SLIDE 36

CMOS NAND Gate

F. Najmabadi, ECE65, Winter 2012

Truth Table v1 = 0 v2 = 0: vo = VDD v1 = 0 v2 = VDD : vo = VDD v1 = VDD v2 = 0 : vo = VDD v1 = VDD v2 = VDD : vo = 0

SLIDE 37

Analysis of CMOS NAND Gate (1)

F. Najmabadi, ECE65, Winter 2012

GS2-KVL GS3-KVL GS4-KVL

GS1-KVL:

1 1

v vGS =

GS2-KVL:

1 2 2 1 2 2 DS GS DS GS

v v v v v v − = → + =

GS3-KVL:

1 3 1 3

v V v v v V

DD SG SG DD

− = → + =

GS4-KVL:

2 4 2 4

v V v v v V

DD SG SG DD

− = → + =

KCL:

4 3 2 1 D D D D

i i i i + = =

DS-KVL:

4 3 1 2 4 SD SD DS DS SD DD

v v v v v V = + + =

3 4 2 1 SD DD SD DD

DS

DS

v

V v V v v v v − = − = + =

SLIDE 38

Analysis of CMOS NAND Gate (2)

F. Najmabadi, ECE65, Winter 2012

2 1 3 4 DS DS SD DD SD DD

v

v v V v V v + = − = − = & Triode in Q4 ON Q4 | | & Triode in Q3 ON Q3 | | ? Q2 OFF Q1

4 4 2 4 3 3 1 3 2 1 1 2 2 1 1 1

= → = → > = − = = → = → > = − = = → − = − = = → → < = =

SD D tp DD DD SG SD D tp DD DD SG D DS DS GS D tn GS

v i V V v V v v i V V v V v i v v v v i V v v ON Q4 | | ON Q3 | | ? Q2 OFF Q1

2 4 1 3 1 1 2 2 1 1 1

→ > = − = → > = − = → − = − = = → → < = =

tp DD DD SG tp DD DD SG DS DS GS D tn GS

V V v V v V V v V v v v v v i V v v ON Q4 | | ON Q3 | | ? Q2 OFF Q1

4 2 4 3 1 3 2 1 1 2 2 1 1 1

= → > = − = = → > = − = = → − = − = = → → < = =

D tp DD DD SG D tp DD DD SG D DS DS GS D tn GS

i V V v V v i V V v V v i v v v v i V v v

For v1 = 0 & v2 = 0, vo = VDD (iD1 = iD2 = iD3 = iD4 = 0)

Case 1: v1 = 0 & v2 = 0

DD SD DD

V

v V v = − =

4

Note: Since vDS1 ≥ 0, we can say vGS2 =vDS1 < Vtn and Q2 is OFF!

4 3 2 1 D D D D

i i i i + = =

SLIDE 39

Analysis of CMOS NAND Gate (3)

F. Najmabadi, ECE65, Winter 2012

2 1 3 4 DS DS SD DD SD DD

v

v v V v V v + = − = − = & Triode in Q4 ON Q4 | | OFF Q3 | | OFF Q2 & Triode in Q1 ON Q1

4 4 2 4 3 1 3 2 1 1 2 2 1 1 1 1

= → = → > = − = = → → < = − = = → → < − = − = = → = → > = =

SD D tp DD DD SG D tp DD SG D tn DS DS GS DS D tn DD GS

v i V V v V v i V v V v i V v v v v v i V V v v

Case 2: v1 = VDD & v2 = 0

DD SD DD

V

v V v = − =

4

ON Q4 | | OFF Q3 | | OFF Q2 ON Q1

2 4 3 1 3 2 1 1 2 2 1 1

→ > = − = = → → < = − = = → → < − = − = → > = =

tp DD DD SG D tp DD SG D tn DS DS GS tn DD GS

V V v V v i V v V v i V v v v v V V v v ON Q4 | | OFF Q3 | | OFF Q2 ON Q1

4 2 4 3 1 3 2 1 1 2 2 1 1 1

= → > = − = = → → < = − = = → → < − = − = = → > = =

D tp DD DD SG D tp DD SG D tn DS DS GS D tn DD GS

i V V v V v i V v V v i V v v v v i V V v v

4 3 2 1 D D D D

i i i i + = =

For v1 = VDD & v2 = 0, vo = VDD (iD1 = iD2 = iD3 = iD4 = 0)