1V sub-100 W 12b all-MOS A/D Converters in the Log-Domain - PowerPoint PPT Presentation

XVII Conference on Design of Circuits and Integrated Systems (DCIS’02) 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain Francisco Serra-Graells paco.serra@cnm.es Wednesday 20th Nov 2002 Institut de Microelectr` onica de Barcelona - Centro Nacional de Microelect´ onica, Spain CENTRE�NACIONAL�DE�MICROELECTRÒNICA IMB

Index 2/23 ◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Introduction to Σ∆ ADC 3/23 Portable and Digital CMOS ◮ mixed SoCs technologies Analog Digital ↓ ↓ §¢ Modulator low-power low-voltage Antialiasing Limiter Filter Decimator Quantizer Σ∆ ADCs all-MOS y in y 0 b out H � 2 (2 L + 1) � M � � 2 L +1 2 N − 1 DR ideal = 3 π DAC 2 π N =1 y 0 y 1 y i y L b out M -oversampling ratio + 1 ¿ f 1 + 1 ¿ fi + 1 ¿ fL 1 1 1 s s s L -order frequency selective H -stage 1 1 1 ¿ b 1 ¿ bi ¿ bL M N -bit quantization y high y dac y low ◮ 1bit → no linearity problems       at Quantizer/DAC 1 − 1 0 0 0 τ f 1 τ b 1       d Y ss 1  0 0     − 1  =  Y ss +  y 0 +  y dac 0       τ fi τ bi d t    1 − 1 0 0 0 ◮ Single-stage → compact circuits τ fL τ bL F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Index 4/23 ◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

All-MOS Log-Domain Proposal 5/23 ◮ Instantaneous Companding theory ◮ MOSFET operating in subthreshold Externally�Linear�Signal�Processing G weak inversion V GB Non-linear y in x in x out y out V SB,DB ≫ V GB − V TO -1 I D Signal�Processing F F n D S DR DR forward saturation < x y DR y DR y V DB V SB Compression Expansion V DB − V SB ≫ U t B VGB − VTO − VSB y = F ( x ) = e x I S = 2 nβU 2 I D = I S e e nUt Ut t F d y i d x i 1 1 τ fi e x i − 1 − x i GD, SD or BD Companding: d t = τ fi y i − 1 ← → d t = F y i = I Di x i = V GBi ← → I S nU t ◮ Pros & cons: • Internal DR V compression → True low-voltage operation √ Compatible with non-linear caps (e.g.MOS) √ → Low-power consumption √ • Subthreshold operation Low-frequency applications (typ. < 1MHz) × F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Index 6/23 ◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Low-Voltage Basic Building Blocks 7/23 I in I lim I 0 I 1 I L b out ◮ CMOS circuit techniques for: + + 2 f c 1 1 1 1 ¼ s +2 f c s s ¿ 1 ¿ L ¼ M • Input compressor and limiter I high I dac • Anti-aliasing filter • Modulator integrator I low • Modulator quantizer I in I lim V lim V 0 V 1 V L b out • Modulator DAC + + + F 1 1 1 1 1 1 G 0 G 1 G L s s s C 0 C 1 C L I high V dac ◮ Target specs: F F I low • Very low-voltage (1V) • Digital Technology (MOS-only) • Audio bandwidth • Low-power (sub-100 µ W) ◮ Application example: Hearing Aids F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Low-Voltage Basic Building Blocks 8/23 ◮ Input compressor V − Vref I ref I = F ( V ) = I ref e I > 0 nUt M4 M5 I in K K 1 Class-A operation: I ref M6 M7 C in � I in � V in = V ref + nU t ln + 1 | I in | < I ref V ref V in M2 M1 I ref Simple frequency compensation: C comp M3 � ζ = 1 KC comp 2 C in • I ref defines full-scale in Class-A • V ref optimizes low-voltage operation • Low input impedance ( < 1KΩ) for optional linear V → I conversion at input F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Low-Voltage Basic Building Blocks 9/23 ◮ Input compressor with limiter  I ref + I in | I in | ≤ I knee  I lim = I ref + I in ± PI knee | I in | > I knee  1 + P I ref I ref piece-wise transfer function: M9 M10 M11 M14 M15 1 P K 1 I in K 1 I lim - I ref I ref - I knee M12 M13 1+ P I lim 1 P I ref + I knee - I knee V lim V ref I in I knee M8 • I knee selects the input threshold • P defines compression ratio F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Low-Voltage Basic Building Blocks 10/23 ◮ Anti-aliasing filter I -domain 1st-order low-pass ODE: M4 M5 d I 0 d t = − 2 πf c I 0 + 2 πf c I lim I tun 0 V -domain non-linear ODE: V lim V 0 M1 M2 I tun 0 I cap 0 d V 0 Vlim − V 0 d t = − 2 πf c nU t + 2 πf c nU t e nUt M3 C 0 Q -domain circuit ODE: d Q 0 d V 0 • Tuning parameter I tun 0 Vin − V 0 = C 0 = − I tun 0 + I tun 0 e nUt d t d t • Thermal cancellation for f c � �� � I cap 0 through PTAT I tun 0 f c = 1 I tun 0 • Non-linear NMOS capacitor C 0 2 π nU t C 0 F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Low-Voltage Basic Building Blocks 11/23 ◮ Modulator Integrator positive τ fi case: I -domain ODE for the τ fi case: M4 M5 d I i d t = 1 I i − 1 τ fi I tunfi V -domain non-linear ODE: V i -1 V i M1 M2 I capi d V i d t = nU t Vi − 1 − Vi e nUt τ fi M3 C i Q -domain circuit ODE: • Tuning parameter I tunfi d Q i d V i Vi − 1 − Vi d t = C i = I tunfi e nUt d t • Thermal cancellation for τ fi � �� � I capi through PTAT I tunfi τ fi = nU t C i • Non-linear NMOS capacitor C i I tunfi Log-mapping (i.e. I > 0) → coefficients only charge xor discharge caps! F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Low-Voltage Basic Building Blocks 12/23 ◮ Modulator Integrator Σ∆ modulator case ( τ fi > 0 τ bi < 0): OP designed at SS-matrix level: I tunfi       V i- 1 V i 1 − 1 0 0 0 ¿ fi 1 1 τ f 1 τ b 1       ¿ bi d I ss 1  0 0     − 1  =  I ss +  I 0 +  I dac I capi 0       τ fi τ bi d t    1 − 1 V dac 0 0 0 C i τ fL τ bL In general, matrix transformation may be required to ensure DC Differential integrator: solution for I > 0. . . Coefficients of the same row � � d Q i d V i Vi − 1 nUt − τ fi − Vi Vdac d t = C i = I tunfi e e e nUt nUt can share half circuitry d t τ bi � �� � I capi F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Low-Voltage Basic Building Blocks 13/23 ◮ Modulator Quantizer I -domain switching scheme: ( I high - I low )  I buffer I low  1 for V L > V ref b out = I ref 0 for V L < V ref  b out V dac V ref b clk b clk b clk V high,low Q b out D V L V ref V -domain switching scheme: I buffer I high I low I ref V high V dac V ref ◮ Modulator DAC b out  � I high �  nU t ln for b out = 1   I ref V dac = V ref + dummies � I low � V low b out  nU t ln for b out = 0   I ref F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Index 14/23 ◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Second-Order Effects 15/23 ◮ Moderate Inversion • e x degradation causes signal distortion 4 10 Strong�Inversion • Wide ( W/L ) to keep devices in deep 2 10 weak inversion even at full-scale 0 Moderate 10 0 I = I -2 D S 10 S V = V +2ln( -1) e nU V + nU I /I » GB TO t TO t D Weak -4 10 -50 /Hz] V = V Moderate GB TO -6 10 rms Inversion 2 I =ln (2) I » I S /2 D S Output�PSD�[dB A -100 ¹ -8 10 -10 10 -150 -20 -10 0 10 20 30 40 ( V -V ) /nU GB TO t VGB − VTO − VSB -200 IC = I D I D = I S e e I S ≪ 1 nUt Ut Quantizer ↓ � � VGB − VTO − VSB -250 I D = I S ln 2 1 + e e 2 nUt 2 Ut 0.1 1 10 100 1000 Frequency�[KHz] F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

Second-Order Effects 16/23 ◮ Thermal Noise . . . block contributions: Equivalent Drain-current noise PSD: 0 d i 2 = 4 KT g ms Dn d f 2 -50 /Hz] Thermal rms Total Output�PSD�[dB A At similar biasing, dominant devices -100 ¹ are those in weak inversion where First Integ. ( g ms /I D ) max : -150 Second d i 2 d v 2 = 2 q ( nU t ) 2 Dn GBn = 2 qI D Third d f d f I D -200 Quantizer Fourth Main blocks are the compressor, anti- -250 0.1 1 10 100 1000 aliasing, 1st integrator and DAC, so: Frequency�[KHz] I ref ≡ I tun 0 ≡ I tunf 1 ≡ I buffer • Class-A operation results in: SNR ∝ +3dB/oct( I ref ) F.Serra-Graells 1V sub-100 µ W 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02