[PPT] - 1V sub-100 W 12b all-MOS A/D Converters in the Log-Domain PowerPoint Presentation

SLIDE 1

XVII Conference on Design of Circuits and Integrated Systems (DCIS’02)

1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain

Francisco Serra-Graells paco.serra@cnm.es

Wednesday 20th Nov 2002

CENTRENACIONALDEMICROELECTRÒNICA IMB

Institut de Microelectr`

nica de Barcelona - Centro Nacional de Microelect´
nica, Spain

SLIDE 2

Index

2/23

◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 3

Introduction to Σ∆ ADC

3/23

◮ Portable and mixed SoCs ↓ low-power Σ∆ ADCs Digital CMOS technologies ↓ low-voltage all-MOS DRideal = 3π

2

2N − 1

2 (2L + 1) M

π

2L+1

M-oversampling ratio L-order frequency selective H-stage N-bit quantization

◮ 1bit → no linearity problems at Quantizer/DAC ◮ Single-stage → compact circuits

H Quantizer DAC Antialiasing Filter y0 bout yin §¢ Modulator Analog Digital Limiter Decimator N=1 bout ydac y1 yL s 1

¿f1

1 +

¿b1

1 yi y0 s 1

¿fi

1 +

¿bi

1 s 1

¿fL

1 +

¿bL

1 M yhigh ylow

dY ss dt =     

1 τfi 1 τfL

     Y ss+     

1 τf1

     y0+      − 1

τb1

− 1

τbi

− 1

τbL

     ydac

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 4

Index

4/23

◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 5

All-MOS Log-Domain Proposal

5/23

◮ Instantaneous Companding theory

yin

Compression

Non-linear SignalProcessing F F

1

Expansion

xin xout yout ExternallyLinearSignalProcessing DR DR

x y

< DRy DRy

y = F(x) = ex

dyi dt = 1 τfiyi−1

F ← →

dxi dt = 1 τfiexi−1−xi

◮ MOSFET operating in subthreshold

VGB VSB VDB ID

D S B G

weak inversion VSB,DB ≫ VGB−VTO

n

forward saturation VDB − VSB ≫ Ut ID = ISe

VGB−VTO nUt

e

− VSB

Ut

IS = 2nβU 2

t

GD, SD or BD Companding: yi = IDi

IS

F ← → xi = VGBi

nUt

◮ Pros & cons:

Internal DRV compression → True low-voltage operation √

Compatible with non-linear caps (e.g.MOS) √

Subthreshold operation

→ Low-power consumption √ Low-frequency applications (typ.<1MHz) ×

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 6

Index

6/23

◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 7

Low-Voltage Basic Building Blocks

7/23

◮ CMOS circuit techniques for:

Input compressor and limiter
Anti-aliasing filter
Modulator integrator
Modulator quantizer
Modulator DAC

◮ Target specs:

Very low-voltage (1V)
Digital Technology (MOS-only)
Audio bandwidth
Low-power (sub-100µW)

bout Idac I1 IL s 1

¿1

+ M 1 s 1

¿L

+ 1 Iin Ihigh Ilow s+2 fc

¼

Ilim I0 bout Vdac VL Iin Ihigh Ilow

F F F

s 1

GL

+ V1 Ilim V0 1

CL

s 1

G1

+ 1

C1

Vlim s 1

G0

+ 1

C0

2 fc ¼

◮ Application example: Hearing Aids

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 8

Low-Voltage Basic Building Blocks

8/23

◮ Input compressor I = F(V ) = Irefe

V −Vref nUt

I > 0 Class-A operation: Vin = Vref + nUt ln Iin Iref + 1

|Iin| < Iref

Simple frequency compensation: ζ = 1 2

KCcomp

Cin

Iin Vin Vref Ccomp Cin

K 1

Iref K Iref

M1 M2 M4 M5 M6 M7 M3

Iref defines full-scale in Class-A
Vref optimizes low-voltage operation
Low input impedance (<1KΩ) for
ptional linear V →I conversion at input

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 9

Low-Voltage Basic Building Blocks

9/23

◮ Input compressor with limiter Ilim =    Iref + Iin |Iin| ≤ Iknee Iref + Iin ± PIknee 1 + P |Iin| > Iknee piece-wise transfer function:

Iin Ilim -Iref Iknee

Iknee

1+P 1

Iin Vlim Vref

K 1

Iref K

M9

Iref -Iknee Iref +Iknee Iref

M10 M11 M14 M15 M12 M13

1 P 1 P

M8

Ilim

Iknee selects the input threshold
P defines compression ratio

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 10

Low-Voltage Basic Building Blocks

10/23

◮ Anti-aliasing filter I-domain 1st-order low-pass ODE: dI0 dt = −2πfcI0 + 2πfcIlim V -domain non-linear ODE: dV0 dt = −2πfcnUt + 2πfcnUte

Vlim−V0 nUt

Q-domain circuit ODE: dQ0 dt = C0 dV0 dt

Icap0

= −Itun0 + Itun0e

Vin−V0 nUt

fc = 1 2π Itun0 nUtC0 V0 Vlim C0 Itun0

M1 M2 M4 M5 M3

Itun0 Icap0

Tuning parameter Itun0
Thermal cancellation for fc

through PTAT Itun0

Non-linear NMOS capacitor C0

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 11

Low-Voltage Basic Building Blocks

11/23

◮ Modulator Integrator I-domain ODE for the τfi case: dIi dt = 1 τfi Ii−1 V -domain non-linear ODE: dVi dt = nUt τfi e

Vi−1−Vi nUt

Q-domain circuit ODE: dQi dt = Ci dVi dt

Icapi

= Itunfie

Vi−1−Vi nUt

τfi = nUtCi Itunfi positive τfi case: Vi Vi-1 Ci Itunfi

M1 M2 M4 M5 M3

Icapi

Tuning parameter Itunfi
Thermal cancellation for τfi

through PTAT Itunfi

Non-linear NMOS capacitor Ci

Log-mapping (i.e. I > 0) → coefficients only charge xor discharge caps!

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 12

Low-Voltage Basic Building Blocks

12/23

◮ Modulator Integrator OP designed at SS-matrix level: dIss dt =     

1 τfi 1 τfL

     Iss+     

1 τf1

     I0+      − 1

τb1

− 1

τbi

− 1

τbL

     Idac In general, matrix transformation may be required to ensure DC solution for I > 0. . . Coefficients of the same row can share half circuitry Σ∆ modulator case (τfi>0 τbi<0): Vi Vdac Ci Itunfi Icapi Vi-1

¿bi

1 1

¿fi

Differential integrator: dQi dt = Ci dVi dt

Icapi

= Itunfie

−Vi nUt

e

Vi−1 nUt − τfi

τbi e

Vdac nUt

F.Serra-Graells

1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 13

Low-Voltage Basic Building Blocks

13/23

◮ Modulator Quantizer bout =    1 for VL > Vref for VL < Vref

Vref VL

D Q bout

bclk bclk bclk

◮ Modulator DAC Vdac = Vref+        nUt ln Ihigh Iref

for bout = 1

nUt ln Ilow Iref

for bout = 0

I-domain switching scheme:

Vdac Vref Ilow Iref (Ihigh-Ilow) Vhigh,low

bout

Ibuffer

V -domain switching scheme:

Vdac Vref Ilow Iref Ihigh Vhigh Vlow

bout bout

dummies

Ibuffer

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 14

Index

14/23

◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 15

Second-Order Effects

15/23

◮ Moderate Inversion

20
10

10 20 30 40 10

10

10

8

10

6

10

4

10

2

10 10

2

10

4

( ) V -V /nU

GB TO t

I /I

D S

StrongInversion Moderate Weak I I

D S

= V V e nU V nU

GB TO t TO t

= +2ln( -1) + » V V

GB TO

= I I

D S

=ln (2)

2

»IS/2

ID = ISe

VGB−VTO nUt

e

− VSB

Ut

IC = ID

IS ≪ 1

↓ ID = IS ln2

1 + e

VGB−VTO 2nUt

e

− VSB

2Ut

ex degradation causes signal distortion
Wide (W/L) to keep devices in deep

weak inversion even at full-scale

0.1 1 10 100 1000

250
200
150
100
50

Frequency[KHz] OutputPSD[dB A /Hz]

rms

¹ Quantizer Moderate Inversion

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 16

Second-Order Effects

16/23

◮ Thermal Noise Equivalent Drain-current noise PSD: di2

Dn

df = 4KT gms 2 At similar biasing, dominant devices are those in weak inversion where (gms/ID)max: di2

Dn

df = 2qID dv2

GBn

df = 2q(nUt)2 ID Main blocks are the compressor, anti- aliasing, 1st integrator and DAC, so: Iref ≡ Itun0 ≡ Itunf1 ≡ Ibuffer . . . block contributions:

0.1 1 10 100 1000

250
200
150
100
50

Frequency[KHz] OutputPSD[dB A /Hz]

rms

¹ Thermal Total First Integ. Second Third Fourth Quantizer

Class-A operation results in:

SNR ∝ +3dB/oct(Iref)

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 17

Second-Order Effects

17/23

◮ NMOS Capacitors Quasi-static Gate-to-Gate NMOS capacitance in all regions (VSB,DB=0): Ci = Coxi

n−1 n

+ 2 √ IC

1 − e−

√ IC

1 + 2 √ IC

1 − e−

√ IC

IC = ln 2

1 + e

Vi−VTO 2nUt

for strong inversion (IC>1):

Ci ≃ Coxi

1 −

Ut Vi − VTO

Non-exact processing:

dQi dt =

Ci + dCi

dVi Vi dVi dt − → dVi dt = Ituni Coxi e

−Vi nUt

1 +

VTOUt (Vi−VTO)2

e

Vi−1 nUt − e Vdac nUt

(
)/

V V Ut

i TO

Weak Inversion

20
15
10
5

5 10 15 20 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 C C

i

xi

/

Strong Inversion

n =2.0 Vi Ci n =1.0

Minimizing non-linearity through

proper biasing: Vref > VTO

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 18

Second-Order Effects

18/23

◮ Waveform Asymmetry Unbalanced DAC symbols: WA . =

1/fs

(Idac0→1 − Ilow)dt −

1/fs

(Idac1→0 − Ihigh)dt 2(Ihigh − Ilow)/fs = 0 First-order model τrise & τfall Null WA conditions:    τfall = τrise I-switching τfall =

Ihigh

Ilow τrise

V -switching When code dependent, WA generates white noise. √ ×

Time Time Vhigh Vlow Ihigh Ilow ¿rise ´ ¿fall ¿ ´ ¿fall

rise

Minimizing WA effects at DAC by: Increasing absolute speed Achieving symbol symmetry Ensuring sequence-independence

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 19

Index

19/23

◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 20

Design Examples

20/23

◮ 3rd- and 4th-order 1bit 64-oversampling Σ∆ ADCs for Hearing Aids:

Iin Vref

D Q bout

bclk Vref Ilow Ihigh Vref Iref/K K 1 Iref Ccomp Cox0 Cox1 Cox3 Itunf0 Itun0 Itunf1 ItunfL Iref

Compressor

bout bout

AntiAlias 1stInteg L-thInteg Quantizer DAC

Vin V0 V1 VL Vdac

◮ Target specs in 0.35µ digital CMOS technology: Supply Voltage 1.0 V

Max. VTON+|VTOP|

1.3 V Input Full-Scale 10 µApp Input Bandwidth 0.1-8 KHz Dynamic Range 73 dB Power Consumption 75 µW Si Area <0.5 mm2 Iref=6µA, Ituniǫ(0.2,6)µA, Coxiǫ(80,500)pF

80
70
60
50
40
30
20
10

10 20

10

10 20 30 40 50 60 70 80

SNR(X),SDR(o)andSNDR(*)[dB]@finp=10Hz

InputAmplitude[dB A ]

rms

¹ SNR()&SNDR()[dB]

Moderate Inversion Limiter Chaos Thermal Noise

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 21

Design Examples

21/23

◮ Prototypes: expected 12b − → <10b . . . due to not modeling WA !!!

500 m ¹

PTAT References 4th-order §¢Modulator 3rd-order §¢Modulator

◮ Proposed solution: return-to-zero (trz) symbols + τbi=trz Ts τfi compensation ↓ code independent WA ◮ High-level models of new designs return good results. . .

WA1010=WA1100=0 code independent WA1010=WA1100=0 code independent WA1010=WA1100=0 code dependent

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 22

Index

22/23

◮ Introduction to Σ∆ ADC ◮ All-MOS Log-Domain Proposal ◮ Low-Voltage Basic Building Blocks ◮ Second-Order Effects ◮ Design Examples ◮ Conclusions

F.Serra-Graells 1V sub-100µW 12b all-MOS Σ∆ A/D Converters in the Log-Domain DCIS’02

SLIDE 23

Conclusions

23/23

◮ Possibility of implementing Σ∆ ADCs in the Log-domain using the MOSFET in weak inversion ◮ Complete set of low-voltage all-MOS basic building blocks ◮ Detailed modeling of main second-order effects ◮ Expected 1V@100µA 12b@8KHz realizations in short for audio SoCs (e.g. HAs) ◮ Circuit technique suitable for digital VLSI technologies . . . Thank you very much for your attention!