A 1.2V 130 A 10-bit MOS-Only Log-Domain Modulator X. Redondo, J. - - PowerPoint PPT Presentation

▶
a 1 2v 130 a 10 bit mos only log domain modulator
SMART_READER_LITE
LIVE PREVIEW

A 1.2V 130 A 10-bit MOS-Only Log-Domain Modulator X. Redondo, J. - - PowerPoint PPT Presentation

May 22, 2023 49 likes •249 views

ISCAS07: A MOS-only Log-Domain Modulator Intro Modulator Blocks Results Conclusions 1/20 A 1.2V 130 A 10-bit MOS-Only Log-Domain Modulator X. Redondo, J. Pallars and F. Serra-Graells System Integration Department

slide-1
SLIDE 1

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 1/20

A 1.2V 130µA 10-bit MOS-Only Log-Domain Σ∆ Modulator

  • X. Redondo, J. Pallarès and F. Serra-Graells

System Integration Department Institut de Microelectrònica de Barcelona Centro Nacional de Microelectrónica - CSIC Spain

May 2007

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-2
SLIDE 2

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 2/20

1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-3
SLIDE 3

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 3/20

1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-4
SLIDE 4

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 4/20

Scenario

Pre-processing §¢ Modulator Analog Digital Decimator H Quantizer DAC ein DSP ADC bout CMOSIC Sensor

Digital compatibility

◮ Very

low-voltage

  • peration

◮ Low-cost

CMOS process: X Double poly-Si cap X MIM cap

◮ Design parameters: L-order, M-oversampling and N-bit.

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-5
SLIDE 5

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 5/20

1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-6
SLIDE 6

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 6/20

Log-domain proposal

◮ Continuous-time current-mode processing: N=1 bout s 1

¿f1

1 +

¿b1

1

Iin

s 1

¿fk

1 +

¿bk

1 s 1

¿fL

1 +

¿bL

1 M

I1 Ik IL IDAC

DAC

Ihigh Ilow

dI SS dt =     

1 τf 2 1 τfk 1 τfL

     I SS +    

1 τf 1

    Iin −    

1 τb1 1 τb2 1 τbk 1 τbL

    IDAC I SS = [I1I2 · · · Ik · · · IL]T

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-7
SLIDE 7

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 7/20

Log-domain proposal

◮ Inner voltage compression: low-voltage & non-linear (MOS) cap bout

Iin

GfL +

V1 Vk VL VDAC Ihigh Ilow

F F F

Vin

GbL

CL

Gfk + Gbk

Ck

Gf1 + Gb1

C1

i = F(v) = ev

◮ Implemented operating MOSFET in subthreshold (w.i.sat.):

ID = ISe

VGB−VTO nUt

e− VSB

Ut

IS = 2nβ W L

  • U 2

t

i = ID IS

F

← → v = VGB nUt

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-8
SLIDE 8

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 8/20

1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-9
SLIDE 9

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 9/20

Input compressor

Iin Vin Vref Ccomp Cpar

P 1

Iref P Iref

M1 M2 M4 M5 M6 M7 M3

I = F(V ) = Iref e

V−Vref nUt

I > 0 Vin = Vref +nUt ln Iin Iref + 1

  • |Iin| < Iref

Note: dashed MOSFETs working in weak inversion.

◮ Reference levels: Iref and Vref ◮ Low-impedance input for

  • ptional linear V /I conversion

◮ Parasitic input cap

compensation: ζ = 1 2

  • PCcomp

Cpar

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-10
SLIDE 10

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 10/20

Differential integrator with built-in DAC

◮ Single coefficient:

dIk dt = 1 τfk Ik−1

F

← → dVk dt = nUt τfk e

Vk−1−Vk nUt

dQk dt = Ck dVk dt

Icapk

= Itunfke

Vk−1−Vk nUt

  • Gfk

◮ Tuning parameter:

Itunfk = nUtCk τfk

Vk Vk-1 Ck Itunfk

M1 M2 M4 M5 M3

Icapk

Gfk +

Vk-1 Vk Ck Icapk ◮ Voltage compression allows grounded NMOS capacitors

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-11
SLIDE 11

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 11/20

Differential integrator with built-in DAC

◮ Multiple coefficients:

dIk dt = 1 τfk Ik−1− 1 τbk IDAC ≡ 1 τfk

  • Ik−1 − τfk

τbk IDAC

  • Icapk = Itunfke

−Vk nUt

  • e

Vk−1 nUt − τfk

τbk e

VDAC nUt

  • ◮ Gain weight ≡ geometrical ratio

◮ Half circuit shared between

integrator coefficients

Vk VDAC Ck Itunfk Icapk Vk-1

¿bk 1 1 ¿fk

Gfk + Gbk

Vk-1 Vk VDAC Ck Icapk

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-12
SLIDE 12

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 12/20

Differential integrator with built-in DAC

◮ In practice, τk .

= τfk ≡ τbk: Icapk = Itunke

−Vk nUt

  • e

Vk−1 nUt − e Vlow,high nUt

  • bout = 0, 1

◮ Current switching DAC:

Icapk = Itunke

−Vk nUt

  • e

Vk−1 nUt − Ilow,high

Iref e

Vref nUt

  • ◮ Fast settling time

◮ Low cross-talk Vk Vref Ck Itunk Icapk Vk-1

1 1 Ilow Iref Ihigh-Ilow Iref

bout

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-13
SLIDE 13

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 13/20

Quantizer

◮ Equivalent 1-bit expander

Vref VL

D Q

bout Áclk

M1 M2

Ibias

M3 M4

Áclk Áclk bout Áclk

Ilow Ihigh

1

IDAC

Waveform asymmetry

◮ Return-to-zero approach ◮ DAC implementation:

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-14
SLIDE 14

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 14/20

Quantizer

◮ Equivalent 1-bit expander

Vref VL

D Q

bout Áclk

M1 M2

Ibias

M3 M4

Áclk Áclk

RTZ

bRTZ1,0

2

bout Áclk bRTZ1,0

Iref Ilow Ihigh

1

IDAC

01 11 01 00 01 00

Waveform asymmetry

◮ Return-to-zero approach ◮ DAC implementation: Vk Vref Ck Itunk Icapk Vk-1

1 1 Ilow Iref I

  • I

high ref

Iref

bRTZ0

I

  • I

ref low

Iref

bRTZ1

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-15
SLIDE 15

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 15/20

1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-16
SLIDE 16

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 16/20

CMOS integration

MOScapacitorarray 200 m ¹ TranslinearMOSFETarray LVDSdriver PTATgenerator

◮ 4th-order 64-times 1-bit

Σ∆ topology

◮ PTAT reference for Itunk ◮ LVDS out for low bulk-noise ◮ Core size:

700µm×1150µm (0.8mm2)

◮ 0.35µm 1-polySi 3-metal

digital CMOS technology

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-17
SLIDE 17

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 17/20

Results

◮ Design parameters:

Vref 0.7 V Iref 7 µA Ilow,high 1, 13 µA Itun1,2,3,4 7, 1, 1, 1 µA C1,2,3,4 1052, 150, 60, 60 pF (W/L)trans

ID µA × 273 1.5 µm µm

◮ Sampled-time

  • ptimal coefficients

◮ 1MHz sampling

frequency

◮ High-value MOS

capacitors

◮ Experimental PSD:

OutputPSD [dB A /Hz]

rms

¹ Frequeny[KHz] 10 50 1 0.1

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60
  • 70
  • 80
  • 90
  • 100

Half full-scale (1.2µAp) & 33% RTZ

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-18
SLIDE 18

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 18/20

Results

◮ Experimental DR:

Iin [dB A ]

rms

¹ 10

  • 60
  • 50
  • 40
  • 40
  • 30
  • 10
  • 20
  • 10

10 20 30 40 50 60 70

Output SNDR [dB]

1kHz input & 8kHz bandwidth

◮ Performance:

Input full-scale 2.2 µAp Input bandwidth 8 kHz Sampling frequency 1 MHz DAC RTZ code 33 % Dynamic range 9-10 bit Supply voltage 1.2 V VTON +|VTOP| 1.2 V Power consumption 160 µW Silicon core area 0.8 mm2

◮ Better results in short

due to lab update

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-19
SLIDE 19

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 19/20

1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona

slide-20
SLIDE 20

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆Modulator Blocks Results Conclusions 20/20

Conclusions

◮ Novel low-voltage MOS-only Σ∆ Modulator ◮ Log-domain & subthreshold MOSFET based ◮ Circuit implementation for all building blocks ◮ Demonstrator in 0.35µm 1-polySi digital CMOS technology

  • X. Redondo, J. Pallarès and F. Serra-Graells

Institut de Microelectrònica de Barcelona