A 1.2V 130 A 10-bit MOS-Only Log-Domain Modulator X. Redondo, J. - PowerPoint PPT Presentation

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 1/20 A 1.2V 130 µ A 10-bit MOS-Only Log-Domain Σ∆ Modulator X. Redondo, J. Pallarès and F. Serra-Graells System Integration Department Institut de Microelectrònica de Barcelona Centro Nacional de Microelectrónica - CSIC Spain May 2007 X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 2/20 1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 3/20 1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 4/20 Scenario Digital compatibility Analog Digital ◮ Very ADC low-voltage Pre-processing Decimator operation §¢ Sensor DSP Modulator ◮ Low-cost CMOS process: CMOS�IC X Double Quantizer poly-Si cap e in H b out X MIM cap DAC ◮ Design parameters : L -order, M -oversampling and N -bit. X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 5/20 1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 6/20 Log-domain proposal ◮ Continuous-time current-mode processing: N =1 I in I 1 I k I L b out + 1 ¿ f 1 + 1 ¿ fk + 1 ¿ fL 1 1 1 s s s 1 ¿ b 1 1 ¿ bk 1 ¿ bL M I high I DAC I low DAC       1 0 0 0 0 1 τ b 1 τ f 1 1 0 0 0 1   dI SS  0     τ f 2  =  I SS +  I in − τ b 2  I DAC     1   1 0 0 0 dt  0   τ fk τ bk 1 1 0 0 0 0 τ fL τ bL I SS = [ I 1 I 2 · · · I k · · · I L ] T X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 7/20 Log-domain proposal ◮ Inner voltage compression : low-voltage & non-linear ( MOS ) cap I in V in V 1 V k V L b out G f 1 G fk G fL + + + F C 1 C k C L G b 1 G bk G bL I high V DAC F I low F i = F ( v ) = e v ◮ Implemented operating MOSFET in subthreshold (w.i.sat.): � W � VGB − VTO e − VSB U 2 I D = I S e I S = 2 n β nUt Ut t L i = I D v = V GB F ← → I S nU t X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 8/20 1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 9/20 Input compressor Note: dashed MOSFETs working in weak inversion. I ref M4 M5 I in P P 1 I ref C par M6 M7 ◮ Reference levels: I ref and V ref ◮ Low-impedance input for V ref M2 M1 V in optional linear V / I conversion C comp M3 ◮ Parasitic input cap compensation : � V − Vref ζ = 1 PC comp I = F ( V ) = I ref e I > 0 nUt 2 C par � I in � V in = V ref + nU t ln + 1 | I in | < I ref I ref X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 10/20 Differential integrator with built-in DAC ◮ Single coefficient: V k- 1 V k G fk + dI k dt = 1 dV k = nU t I capk Vk − 1 − Vk F ← → I k − 1 e nUt C k τ fk dt τ fk dQ k dV k Vk − 1 − Vk = C k = I tunfk e nUt dt dt � �� � � �� � M4 M5 G fk I capk I tunfk ◮ Tuning parameter: V k -1 V k I tunfk = nU t C k M1 M2 I capk τ fk C k M3 ◮ Voltage compression allows grounded NMOS capacitors X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 11/20 Differential integrator with built-in DAC ◮ Multiple coefficients: V k- 1 V k G fk + � � I capk dI k dt = 1 I k − 1 − 1 I DAC ≡ 1 I k − 1 − τ fk G bk I DAC V DAC C k τ fk τ bk τ fk τ bk � � nUt − τ fk − Vk Vk − 1 VDAC I capk = I tunfk e e e nUt nUt τ bk I tunfk ◮ Gain weight ≡ geometrical ratio V k- 1 V k ◮ Half circuit shared between ¿ fk 1 1 ¿ bk integrator coefficients I capk V DAC C k X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 12/20 Differential integrator with built-in DAC ◮ In practice, τ k . = τ fk ≡ τ bk : � � Vk − 1 Vlow , high − Vk nUt − e I capk = I tunk e b out = 0 , 1 e nUt nUt ◮ Current switching DAC: � � Vk − 1 nUt − I low , high Vref − Vk I capk = I tunk e e e nUt nUt I ref I low I ref b out I tunk ◮ Fast settling time V k- 1 V k 1 1 ◮ Low cross-talk I capk V ref C k I high -I low I ref X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 13/20 Quantizer Waveform asymmetry ◮ Equivalent 1-bit expander ◮ Return-to-zero approach Á clk Á clk ◮ DAC implementation: M3 M4 Á clk b out D Q V L V ref M1 M2 I bias Á clk b out 1 0 0 I high I DAC I low X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 14/20 Quantizer Waveform asymmetry ◮ Equivalent 1-bit expander ◮ Return-to-zero approach Á clk Á clk ◮ DAC implementation: M3 M4 Á clk b out D Q V L V ref M1 M2 RTZ b RTZ 1,0 2 b RTZ 0 b RTZ 1 I bias I low I ref I tunk Á clk V k- 1 V k 1 1 b out 1 0 0 I capk V ref b RTZ 1,0 C k 11 01 00 01 00 01 I -I I -I ref low high ref I high I ref I ref I ref I DAC I low X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 15/20 1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 16/20 CMOS integration MOS�capacitor�array ◮ 4th-order 64-times 1-bit Σ∆ topology ◮ PTAT reference for I tunk ◮ LVDS out for low bulk-noise ◮ Core size: 700 µ m × 1150 µ m ( 0.8mm 2 ) ◮ 0.35 µ m 1-polySi 3-metal digital CMOS technology PTAT�generator 200 m LVDS�driver ¹ Translinear�MOSFET�array X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 17/20 Results ◮ Design parameters : ◮ Experimental PSD : 0.7 V V ref I ref 7 µ A 0 0 I low , high 1, 13 µ A I tun 1 , 2 , 3 , 4 7, 1, 1, 1 µ A -10 C 1 , 2 , 3 , 4 1052, 150, 60, 60 pF ID µ A × 273 µ m -20 ( W / L ) trans 1 . 5 µ m /Hz] -30 rms Output�PSD [dB A -40 ◮ Sampled-time ¹ -50 optimal coefficients -60 ◮ 1MHz sampling -70 frequency -80 ◮ High-value MOS -90 capacitors -100 0.1 1 10 50 Frequeny�[KHz] Half full-scale (1.2 µ A p ) & 33% RTZ X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 18/20 Results ◮ Experimental DR : ◮ Performance : Input full-scale 2.2 µ A p 70 Input bandwidth 8 kHz Sampling frequency 1 MHz 60 DAC RTZ code 33 % Dynamic range 9-10 bit 50 Supply voltage 1.2 V V TON + | V TOP | 1.2 V Output SNDR [dB] 40 Power consumption 160 µ W 0.8 mm 2 Silicon core area 30 ◮ Better results in short 20 due to lab update 10 0 -10 -60 -50 -40 -40 -30 -20 -10 0 10 I in [dB A ¹ ] rms 1kHz input & 8kHz bandwidth X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona

ISCAS’07: A MOS-only Log-Domain Σ∆ Modulator Intro Σ∆ Modulator Blocks Results Conclusions 19/20 1 Introduction 2 Log-Domain System Proposal 3 Low-Voltage All-MOS Building Blocks 4 Integration and Results 5 Conclusions X. Redondo, J. Pallarès and F. Serra-Graells Institut de Microelectrònica de Barcelona