[PPT] - Design of DC-DC Converters Frank Xi fxi@monolithicpower.com PowerPoint Presentation

SLIDE 1

Design of DC-DC Converters

Frank Xi

fxi@monolithicpower.com

Monolithic Power Systems Inc. IEEE SSCS Dallas Chapter, October 2007

SLIDE 2

11/1/2007 IEEE SSCS - Oct. 2007 2

Design of DC-DC Converters

DC-DC Converter Basics

Topology and Operation of DCDC Converters Control Scheme for DCDC

DC-DC Converter Design Techniques

System Level Modeling and Design Building Block Design Considerations

SLIDE 3

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DC-DC Converter Basics

DC-DC Converter is a Voltage Regulator

Use Switches, Inductor and Capacitor for

Power Conversion

Switched Mode Operation

Why DC-DC Converters?

High Efficiency Can Step-Down, Step-up, or Both, or Invert Can Achieve Higher Output Power

SLIDE 4

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DC-DC Converter Basics

Why not DC-DC Converters?

Complex Control Loop Higher Noise and Output Ripple More External Components

Basic DC-DC Converter Topologies

Majority of DC-DC uses PWM Control

Operated in CCM Mode

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DC-DC Converter Basics

Basic Relationships

CCM Mode

IL always supplies load IC small, independent of

load

DCM Mode

IN IN O ON ON OUT

V V T L I T T V ⋅ ⋅ + = 2

2 2

OUT IN IN IN ON OUT

I D I V D V T T V ⋅ = ⋅ = =

Step-down (Buck)

L C S D VSW VOUT VIN IL IC VSW IL IO IO VOUT IIN TON T Continuous Conduction Mode (CCM) ID IIN ID IL Discontinuous Conduction Mode (DCM) IO

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DC-DC Converter Basics

Step-up (Boost)

Basic Relationships

CCM Mode

IL only supplies load during

TOFF period

IC large and load dependent

DCM Mode

IN ON IN O ON OUT

V T V T L I T V

2 2

2 ⋅ ⋅ + =

OUT L IN IN IN OFF OUT

I D I I V D V T T V ⋅ − = = ⋅ − = = 1 1 1 1

L C S D VSW VOUT VIN IL IC VSW IL

IO

IO VOUT TON T Continuous Conduction Mode (CCM) IC IL

IO

Discontinuous Conduction Mode (DCM) IC TOFF

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Common Control Architectures

Modulation Scheme

PFM (Pulse-Frequency-Modulation)

Pulse Skipping, Hysteretic, Constant-on etc. High Efficiency at Light Load Inherently Higher Output Ripple Unmanaged Spectrum Noise

PWM (Pulse-Width-Modulation)

Fixed Frequency with Variable Duty Cycle Better Transient Response (except Hysteretic?) Most Widely Used

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Common Control Architectures

Control Method (for PWM)

Voltage Mode

Regulates Output Voltage by Adjusting Duty Cycle Constant Ramp for Modulation, Better Noise

Immunity

LC Filter Contributes to Complex Conjugate Poles Loop Has No Information on Inductor Current Slower Response to Input Voltage Change Bandwidth Varies with Input Voltage Current Limit Done Separately

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Common Control Architectures

Current Mode

PCM (Peak-Current-Mode) Most Commonly Used Regulates Inductor Current to Satisfy Load

Demand and Maintain Output Voltage

Fast Current Loop makes Inductor to be a VCCS,

eliminates Complex Conjugate Poles

Easy Built-in Cycle-to-Cycle Current Limit Naturally Suitable for Multi-Phase Operation Current Sense Susceptible to Noise Need Slope Compensation for >50% Duty Cycle

Operation

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DC-DC Converter Design

Examples of Common DC-DC Converters

Voltage Mode Buck

L C S1 VSW RESR RL S2 R1 R2 VREF VRAMP S R Q QB CLK VFB VEA VOUT VIN CLK VRAMP VEA VSW VOUT IL IOUT D D’ EA RST

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Voltage Mode Buck

Voltage Mode Buck Transfer Functions:

amplifier error the

f

function transfer the is where and ) ( ) ( 1 1 1 , 1 1 ) 1 ( 1 ) ( ) 1 (

2 2 2

s a s a V v d L C R C L R Q LC s Q s sCR V CR R L s LC s sCR V d v

R FB ESR L ESR IN ESR L ESR IN O

= + = = + + + = + + + + ≈ ω ω ω

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Voltage Mode Buck

Example: L=2.2uH, C=22uF, RESR=10m Ohm VIN=5V, VOUT=3.3V RL=10 Ohm FSW=1.5MHz VRAMP=100mV ω0 = 22.9kHz Q = ~15.8 ωZ = 700kHz

Control (Duty Cycle) to Output Transfer Function:

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Voltage Mode Buck - Error Amp Ex. 1

2 2 1 2 1 2 1 2

1 ) 1 ( ) ( ω ω s Q s sCR V V R R LG v R R v V V R R V V

ESR R IN FB EA FB REF REF EA

+ + + ⋅ − = − = − + =

Use low DC gain to set the bandwidth so that the phase margin is acceptable:

Bandwidth: ~400kHz Phase margin: ~35° Conditionally stable

Example: R2=500k, R1=100k, VR=100mV

Closed loop step response EA VREF VFB R1 R2 VEA

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Voltage Mode Buck - Error Amp Ex. 1

Some Improvements Can Be Added:

Make VRAMP proportional to VIN -> Constant

Bandwidth

Add Feed-forward Cap on Feedback Resistor String

> better phase margin

Limitations of Low DC Gain:

Loose Output Regulation Need some ESR to Stabilize the Loop Small Modulation Ramp Sensitive to Noise DC Offset if Output Cap has large ESR

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Voltage Mode Buck - Error Amp Ex. 2

Use Type-III Compensation Network to Re-Shape Loop Frequency Response:

LC V V C R UGBW s Q s sCR V V C sR C sR C A sR C sR R sC A LG C C sR C sR C C A sR C R R s R sC A v v

R IN ESR R IN FB EA

1 1 ) 1 ( ) 1 )( 1 ]( 1 [ ) 1 )( 1 ( ) || 1 )( 1 )]( )( 1 ( 1 [ ] ) ( 1 )[ 1 (

2 1 2 2 3 1 2 2 1 3 2 3 1 1 1 3 1 2 2 3 1 3 2 2 3 1 1

⋅ ⋅ ≈ + + + ⋅ + + + + + − ≈ + + + + + + + + − ≈ ω ω

High DC gain rolls off by dominant pole and,

phase shift recovered by 1st zero before ω0

2nd zero brings back phase shift above ω0
2nd and 3rd pole attenuates high frequency noise

Example Design Steps:

1. Set R1C2=100uS for desired

BW of ~300kHz

2. Set 1st zero to be 1/5 of ω0:

R1=1Meg, C1=30pF, ωz1=5.3kHz

3. Set 2nd zero to be 4x of

ω0: C2=10pF, R3=200k, ωz2=79.5kHz

4. mid-band DC gain of 5:

R3=200k

5. Set 2nd and 3rd pole to near

switching frequency for high frequency noise attenuation: C3=0.2pF, ωp2=795kHz; R2=10k, ωp3=1.5MHz

EA VREF VFB VEA R3 R2 R1 C2 C1 C3

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Voltage Mode Buck - Error Amp Ex. 2

Modulation ramp VRAMP increased to

500mV for better noise immunity

Blue: control to output transfer function
Green: Type-III compensation error

Amp transfer function

Red: Complete loop transfer function

bandwidth: ~340kHz, PM: ~65 degree

Compare to Error Amp Ex. 1:

Step response has less overshoot

due to better phase margin

Settling is much slower due to 1st

zero at low frequency

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DC-DC Converter Design

Current Mode Buck (Peak Current Control)

L C S1 VSW RESR RL S2 R1 R2 VREF VRAMP S R Q QB CLK VFB VEA VOUT VIN CLK VRAMP VEA VSW VOUT IL IOUT D D’ EA Slope Comp RSEN RST RST

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Current Mode Buck

correction cycle 1 , stable guaranteed , 2 : ex 1 that so chosen is ) ( ] [ ] 1 [

2 2 1 2 1 2

m m m m m m m m m m m m m n i n i

a a a a a a a e e

= = < + − + − − ⋅ = +

Inductor Current Instability for Duty Cycle > 50%:

Requires Slope Compensation:

cycles

ver

grows : 1 cycles

ver

attenuates : 1 ] [ ) ( ] [ ] 1 [

1 2 1 2 1 2 1 2 e e n e e e

i m m i m m m m i m m n i n i > < ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛− ⋅ = − ⋅ = +

m1 m2 m1 m2 ma ie[n] ie[n+1] ie[n] ie[n+1] ie[n+1] ie[n]

1. D=1/3: m2/m1=1/2
2. D=2/3: m2/m1=2
3. D=2/3 with slope compensation

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Current Mode Buck

Fast current loop regulates inductor peak current, can

be modeled as a VCCS with output impedance Rx

Slower voltage loop provides reference for current loop

) 1 ( 2 1 1 2 5 . ) 1 )( 1 ( 1 2 1 1 1 1 1 ) ( 1 1 1 ] 5 . ) 1 )( 1 [( 1 1 1 ) ( 1 1 1 ) ( ] 5 . ) 1 )( 1 [( 1 1 1 ] 5 . ) 1 )( 1 [( 1 1 1

2 1 2 2 1 1 2 1 1

m m D D m m Q s Q s R R R s G sT e e D m m L T R R s G m m m m sT e e s H D m m T L R R R R D m m L T R R v i G

a a S S X L SEN m S sT sT a S L SEN m a a S sT sT e a S X X L SEN a S L SEN EA

m

S S S S

− − = − − + = + + + ≈ − ⋅ + + − − + + = + − = − ⋅ + + = − − + = + = − − + + = =

− − − −

π π ω ω α α α α α : response frequency including ctance transcondu VCCS Complete where : effect sampling and delay in results Operation Switched where

C RESR RL R1 R2 VREF VFB VEA VOUT VIN EA Gm IO RX

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Current Mode Buck

Example: L=2.2uH, VIN=5V, VOUT=3.3V, RL=10 Ohm RSEN = 0.5 Ohm FSW = 1.5MHz Blue: ma=0.5*m2 RX=19.4 Ohm Gm=1.32 A/V Q=1.87 Green: ma=m2 RX=6.6 Ohm Gm=0.80 A/V Q=0.64

Peak Current Mode Current Loop Transfer Function

SLIDE 21

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Current Mode Buck

Control to Output Transfer Function Equivalently Single-Pole System with Current Source Input

)] || ( 1 [ 1 ) ( 1 1 1 1

2 X L ESR S S X L SEN L O m EA

R

R sC sCR s Q s R R R R Z G v v + + + + + = ⋅ = ω ω

Example: C=22uF, RESR=10m Ohm RSEN = 0.5 Ohm FSW = 1.5MHz RX=19.4 Ohm RL=10k, 1k, 100, 10, 1 Ohm

RL=10k, 1k, 100, 10, 1 Ohm

SLIDE 22

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Current Mode Buck – Error Amp

Error Amplifier Example:

impedance

utput

the is amp error the

f

ctance transcondu the is : where

m

C Z Z

m
C

Z C FB EA

r g C C R sC R r R g r sC R sC A v v s a ) ( ) 1 )]( ( 1 [ 1 ) (

1 1 1

>> + + + + + − ≈ =

EA VREF VFB R1 RZ VEA CC C1 ie

Bandwidth defined by R1 and C1
Much smaller CC, need large RZ
VFB more error during transient

Example: gm=100uS, ro=10MOhm, R1=100kOhm, CC=25pF, RZ=1.5MOhm, C1=0.3pF

SLIDE 23

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Current Mode Buck – Error Amp

C R R R BW R R C s R s LG LG BW

SEN Z Z BW SEN BW

1 2 1 1 1 1 | ) ( | : 1 |

1 1

π = = ⋅ ⋅ ≈ = | setting by

btained

Complete Loop Transfer Function of Current Mode Buck:

) 1 )]( ( 1 [ 1 )] || ( 1 [ 1 ) ( 1 1 1 1

1 1 2 Z Z

m
C

Z C X L ESR S S X L SEN L

R sC R R r g r sC R sC A R R sC sCR s Q s R R R R LG + + + + + ⋅ + + ⋅ + + + − = ω ω

1st zero of error amp placed

near output filter pole

ESR zero and 2nd pole of

error amp are placed out of loop bandwidth

SLIDE 24

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DC-DC Converter Design

Voltage Mode Boost

L C S2 VSW RESR RL R1 R2 VREF VRAMP S R Q QB CLK VFB VEA VOUT VIN CLK VRAMP VEA VSW VIN IL IOUT D D’ EA S1 D RST

SLIDE 25

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Voltage Mode Boost

Voltage Mode Boost Transfer Functions:

amplifier error the

f

function transfer the is where and ) ( ) ( 1 ) 1 ( ) 1 ( 1 1 , ) 1 ( , ) 1 ( 1 ) 1 )( 1 ( ) 1 ( 1 ) ) 1 ( ( ) 1 ( ) ) 1 ( 1 )( 1 ( ) 1 (

2 2 2 2 2 2 2 2 2

s a s a V v d L C R D C L R D Q L D R LC D s Q s s s D V CR D R L s D LC s D R L s sCR D V d v

R FB ESR L L RHP RHP Z IN ESR L L ESR IN O

= − + − = − = − = + + − + − = + + − + − − − + − ≈ ω ω ω ω ω ω

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Perturbation from Output to Inductor Current:

2

) 1 ( D sL i v Z

O

− = = ) 1 ( ) 1 ( ) 1 ( ) 1 ( D i i D I I sL v D i V D V dt di L

L

L

O

L

O IN L

− = ⇒ − = − = ⇒ − − = and

Impedance looking into the Inductor from Output: Thus the Effective Inductance

2

) 1 ( D L Leff − =

This makes the ω0 of the LC Filter to Move with D

Voltage Mode Boost - Effective Inductance

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Voltage Mode Boost - RHP Zero

Perturbation from Duty Cycle to Output Current:

sL V d i V V D DV dt di L D I d D i I d D i i D I I

O L O IN IN L O L L L

L

O

⋅ ≈ ⇒ − − + = − ⋅ − − = ⋅ − − = ⇒ − = ) )( 1 ( 1 ) 1 ( ) 1 ( ) 1 (

Right-Half-Plan Zero forms at frequency where:

L D R D I d D L j V d

L RHP O RHP O 2

) 1 ( | 1 | | ) 1 ( | − = − ⋅ = − ⋅ ω ω

Right-Half-Plan Zero exists for both Voltage Mode and Current Mode Boost

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Voltage Mode Boost

Example: L=2.2uH, C=10uF, RESR=10m Ohm, VIN=2.5V, VOUT=5V, 10V, 15V, IOUT=100mA FSW=1.5MHz ω0 and ωRHP moves lower with increased duty cycle

Control (Duty Cycle) to Output Transfer Function:

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Voltage Mode Boost – Type-III Error Amp

Usually Type-III Compensation Network is Required:

LC V V C R BW LC s V V C R BW s Q s s s D V V C sR C sR C A sR C sR R sC A LG C C sR C sR C C A sR C R R s R sC A v v

R IN BW R IN RHP Z RHP Z R IN FB EA

⋅ ⋅ = ⇒ = ⋅ ⋅ + + − + − ⋅ + + + + + − ≈ + + + + + + + + − ≈

2 1 2 1 2 2 2 3 1 2 2 1 3 2 3 1 1 1 3 1 2 2 3 1 3 2 2 3 1 1

2 1 1 1 : 1 ) 1 )( 1 ( ) 1 ( ) 1 )( 1 ]( 1 [ ) 1 )( 1 ( ) || 1 )( 1 )]( )( 1 ( 1 [ ] ) ( 1 )[ 1 ( π ω ω ω ω ω ω : and than lower be to BW Set

EA VREF VFB VEA R3 R2 R1 C2 C1 C3

Example Design Steps:

1. Estimate worst case

ωRHP=300kHz

2. Set BW<100k:

R1C2<2.75µs

3. Set both zeros near ω0:

R1=100k, C1=100pF, R3=300k, C2=20pF, ωz1=16.0kHz, ωz2=26.5kHz

4. Bandwidth: fBW= 80kHz
5. Mid-band DC gain of 1/3
6. Set 2nd and 3rd pole to

beyond ωRHP : R2=10k, C3=3pF ωp2=530kHz, ωp3=790kHz

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Voltage Mode Boost – Type-III Error Amp

Phase shift exceeds 180° at

ω0 -> conditionally stable

Move 1st zero lower to

improve phase shift -> much larger C1

Adjust C1 to move 1st zero
Adjust R3 to move 2nd zero and

mid-band gain

2nd pole and 3rd poles suppress

high frequency noise

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DC-DC Converter Design

Current Mode Boost

C S2 VSW RESR RL S1 R1 R2 VREF VRAMP S R Q QB CLK VFB VEA VOUT VIN CLK VRAMP VEA VSW VIN IL IOUT D D EA Slope Comp RSEN RST L D’ RST

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Current Mode Boost

) 1 ( 2 1 1 2 5 . ) 1 )( 1 ( 1 2 1 1 2 1 1 1 ) ( ) 2 || ] 5 . ) 1 )( 1 [( ( ) 1 ( 1 2 1 1 1

2 1 2 2 1 2

m m D D m m Q T s Q s R R R D s G DT L D m m T L D R R R R D v i G

a a S S S S X L SEN m S a S X X L SEN EA

m

− − = − − + = = + + + − ≈ − − + − = + − = = π π π ω ω ω : system pole

2

a in results effect sampling and Delay Buck Mode Current Peak to Similar where

C RESR RL R1 R2 VREF VFB VEA VOUT VIN EA Gm IO RX

Transfer Function of the Current Loop:

SLIDE 33

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Current Mode Boost

Control to Output Transfer Function:

L D R R R sC s sCR s Q s R R R R D Z s G v v

L RHP X L ZRHP ESR S S X L SEN L O m EA

2

2

) 1 ( )] || 2 ( 1 [ ) 1 )( 1 ( ) ( 1 1 2 1 1 2 ) 1 ( ) ( − = + − + ⋅ + + + − = ⋅ = ω ω ω ω

Example: VIN=2.5V VOUT= 5V, 10V, 15V, 20V L=2.2uH, C=10uF RESR=10m Ohm IOUT = 100mA RSEN = 0.5 Ohm FSW = 1.5MHz

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Current Mode Boost – Error Amp Ex.

) 1 )]( ( 1 [ 1 )] || 2 ( 1 [ ) 1 )( 1 ( ) ( 1 1 2 1 1 2 ) 1 ( ) (

1 1 2 Z Z

m
C

Z C X L ZRHP ESR S S X L SEN L

R sC R R r g r sC R sC A R R sC s s sCR s Q s R R R R D s T + + + + + ⋅ + − + ⋅ + + + − − = ω ω ω

Use the same error amp structure as on page 22: The Complete Loop Transfer Function: Generally Guideline:

To ensure loop stability, the unity-gain bandwidth is set to be

3-5x lower than the worst case RHP zero

The ESR zero and 2nd pole of the amplifier is placed higher than

the RHP zero

The current loop poles are usually much higher than RHP zero

EA VREF VFB R1 RZ VEA CC C1

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Current Mode Boost – Error Amp Ex.

Loop Bandwidth can be estimated as:

) 1 ( ) ( ) 1 ( 3 ) 1 ( 2 1

2 2 2 1

D BW , I V V V V R D R R R C R D BW

O O IN O IN L L RHP RHP Z SEN

− ∝ ⋅ = = − ∝ < ≤ ⋅ − = Since shift) phase 18 s contribute zero (RHP

ω

ω π

Bandwidth should be set at max. duty cycle and load Example:

VIN=2.5V, VOUT=5V, IO=500mA L=2.2uH, C=10uF, RSEN=0.5 Ohm, RZ=1M Ohm, ωZRHP=181kHz, BW chosen to be ~60kHz Calculate: R1:~300k Ohm

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Current Mode Boost

Error Amplifier Example: R1=250k, RZ=1M CC=25pF, C1=0.3pF Output Current: 1mA, 10mA, 100mA, 500mA Loop BW: ~60kHz

Complete Loop Transfer Function of Current Mode Boost Converter:

SLIDE 37

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DC-DC Converter – Building Blocks

PWM Comparator

Multi-Stage Gain -> Faster For Small Input Signal But, High-Gain Stage Has Longer Recovery Time So, Usually Low-Gain Amp(s) Followed by High-Gain

Comparator

SLIDE 38

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Building Blocks – PWM Comparator

OTA based comparator with pre-amps

INP INN COMP OUT

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Building Blocks – Error Amplifiers

Good:

Input Common Mode Down

to Ground

Smaller Input Offset than

OTA But:

Difficult to get large Gm

INP INN OUT BIAS

Error Amplifiers

Folded-Cascode Error Amplifier

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Building Blocks – Error Amplifiers

Good:

Constant Gm Defined by R
Scalable Gm by Current

Mirrors But:

Higher Input Offset due to

Even More Current Mirrors

Additional Gm Regulation

Loop

Constant Gm Error Amplifier

INP INN I1 I1 I2 I2 R OUT

SLIDE 41

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