Power Converters Control Technique 10.1 The Dynamic Problem 10.2 - - PDF document

SLIDE 1

1

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 1]

10.1 The Dynamic Problem 10.2 Control

• 10.2.1 Modulator
• 10.2.2 Oscillator
• 10.2.3 Isolation

10.3 Design of feedback system 10.4 Frequency response of power converter

• 10.4.1 Average Model – AC Analysis
• 10.4.2 SPICE Linearization
• 10.4.3 Example: Frequency response of the BUCK converter

10.5 Voltage Mode 10.6 Current Mode

• 10.6.1 Current feedback
• 10.6.2 Peak Current Mode (PCM) and Average Current Mode (ACM)

10.7 Parasitic Effects

• 10.7.1 PCB trace resistance
• 10.7.2 Correct layout
• 10.7.3 Interfering signal injection
• 10.7.4 Inductive coupling
• 10.7.5 Stray inductance

Power Converters Control Technique

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 2]

The Dynamic Problem

A closed loop converter is a feedback system Issues:

Stability Rejection of input voltage variations (audio

susceptibility)

Resistance to load changes Quick response to reference change - good

• tracking. Important for variable output voltage

working in close loop.

SLIDE 2

2

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 3]

The Dynamic Problem

Power stage Feedback Vo Vref +

• D

Power stage is a Switching system Feedback is analog (or digital) control

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 4]

Power stage Vref

+

• MOD

R1 R2 Ve D

m

β

e

β Vo vo d ve

( )

Function log Ana f v v

e

• −

Feedback factor ve (small signal) into d (small signal)

Closed Loop

SLIDE 3

3

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 5]

t t Zoom Ve D t d D d is the AC component of D

The Concept of d

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 6]

Control

The power conversion system

( power ) Duty cycle Feedback ( power ) Power stage Vin VO RO CO

Driver k error amp VO PWM modulator Ve Vref

SLIDE 4

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 7]

Modulator

Ve +

• Vv

comp Vp Ve

( )

v s v p t

V T t V V V + − =

( )

v s

• n

v p e t

V T t V V V V + − = =

( )

v p v e

• n

s

• n

V V V V D T t − − = = Practical Don max ≈ 0.8 ÷ 0.9

D 1 Vv Vp Ve

Oscillator

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 8]

Oscillator

SLIDE 5

5

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 9]

Complete controller - Voltage Mode (VM)

This controller does not include an error amplifier

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 10]

Primary to secondary isolation

The problem :

Filter Converter RO VO D Isolation barrier

SLIDE 6

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 11]

Feedback Alternatives

isolation

• V

Power stage feedback

ref

V

in

P

• +

Power stage

ref

V

• +

D feedback isolation

• V

A B

isolation Power stage feedback

• V

Gain

• ref

V

+

isolation Power stage

• ref

V

+

+ Gain feedback D D

• V

C D

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 12]

A1 KR Vo Vref

1

β

R 1 1 1 1 ref

• K

A 1 A V V β + β = ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ 1 K A

R 1 1

> β

R ref

• K

1 V V = ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛

Output Voltage Sampler

SLIDE 7

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 13]

Vref ) f (

1

β ) f ( A1 KR Stability and dynamic response depend on Loop Gain (LG)

( ) ( )

f A f K LG

1 1 Rβ

= General representation

( ) ( )

f f A LG β =

LoopGain

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 14]

Bode Plot

f f

• φ

db +180 |LG|

( ) ( )

f A f β In negative feedback systems At f→0 ) 180 ( 180

• −

= φ

SLIDE 8

8

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 15]

) s ( LG 1 ) s ( A ACL + =

The system is unstable if {1+LG(s)} has roots

in the right half of the complex plane.

Nyquist criterium is a test for location of

{1+LG(s)} roots.

Nyquist criterium is normally translated into

the Bode plane (frequency domain)

Nyquist Criterion

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 16]

f f

• φ

db

• 180

A β

m

ϕ 180o already substracted 1 A = β

• 1

| A |

• 1

| A | m

180 ) 180 ( + ϕ = − − ϕ = ϕ

= β = β

Bode Presentation

SLIDE 9

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 17]

The design problem

Given A(f) Find β(f)

( )

A log 20 ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ β 1 log 20

( )

⎟ ⎠ ⎞ ⎜ ⎝ ⎛ β = 1 log 20 A log 20 | A | β f 1 A = β

( ) ( )

A log 20 1 log 20 A log 20 β = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ β −

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 18]

f db 1 β 1 A = β A db = β db A | A | β | A | β

LG=1

SLIDE 10

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 19]

f dec db 20 + dec db 20 − dec db 40 − dec db 20 −

db

A β rate of closure

If rate of closure system is stable

dec db

20 −

f

dec db dec db

20 −

dec db

40 −

dec db

60 −

db

A s s s s u u

( ) db

f 1 β

dec db

20 +

dec db dec db

20 −

dec db

40 −

Rate of Closure

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 20]

f |A| β 1

• m

90 = ϕ

• m

45 = ϕ

• m

90 = ϕ

• m

45 = ϕ

• m

90 = ϕ

• m

45 = ϕ t Close loop Bandwidth f shift Not important as low as possible

| A | β

as large as possibe DC error

Bandwidth

SLIDE 11

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 21]

• m

40 Choose > ϕ

t f M Overshoot M Overshoot

m

ϕ

m

ϕ

• 60

Exitation

Phase Margin Effects

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 22]

f |A| β 1

• m

90 = ϕ

• m

45 = ϕ

• m

90 = ϕ

• m

45 = ϕ

• m

90 = ϕ

• m

45 = ϕ t Close loop Bandwidth f shift Not important as low as possible

| A | β

as large as possibe DC error

DC LG

SLIDE 12

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 23]

f β 1 f

dec db

20 − β f1 f2 A0 A2

Lag Lead

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 24]

L

• C
• R

in

V

• V

L

I

in

E

b

G S L

• C
• R

in

V D

• V

Polarity: (voltage and current sources) selected by inspection

L

• in

V V E → −

• n

in in

D V E ⋅ =

• n

L b

D I G ⋅ =

Average Model – AC Analysis

SLIDE 13

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 25]

Linearization

R V(in) I(3)

• ut

) 3 ( I ) in ( V )

• ut

( V ∗ = ) 3 ( i )) 3 ( I ( ))

• ut

( V ( ) in ( v )) in ( V ( ))

• ut

( V ( ))

• ut

( V ( d ∂ ∂ + ∂ ∂ = ) 3 ( i ) 3 ( I )

• ut

( V ) in ( v ) in ( V )

• ut

( V )

• ut

( V ∆ ∆ + ∆ ∆ =

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 26]

SPICE Linearization (AC Analysis)

) 3 ( I ) in ( V F = ∆ ∆

R V(in) I(3)

• ut

R

• ut

) 3 ( i ) 3 ( I F

• ⋅

⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ∆ ∆

) in ( V ) in ( V F

• ⋅

⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ∆ ∆

) in ( V ) 3 ( I F = ∆ ∆

SLIDE 14

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 27]

Buck linearization

L

• C
• ut

in

V

L

I

b

G

in

E

in

• R

D I G

L b =

D V E

in in =

• ut
• in

D E ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ∆ ∆

• in

in

V E ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ∆ ∆ L Vin ) in ( v ) d ( V

0 ⋅

) d ( v ) in ( V

0 ⋅

in

• b

D G ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ∆ ∆

• L

b

I G ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ∆ ∆ ) d ( v ) L ( I

0 ⋅

) L ( i ) d ( V

0 ⋅ L

I Co Ro

D

V VAC d R

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 28]

Example: Buck Average Model Simulations

Gc V(Doff)*I(Lout)/(V(Don)+V(Doff)) GVALUE

OUT+ OUT- IN+ IN-

EL V(Don)*V(a,b)+V(Doff)*V(a,c) EVALUE

OUT+ OUT- IN+ IN-

PARAMETERS: FS = 100k TS = {1/fs} Vin {Vin}

+

• a

RLoad {RLoad} Doff Lout {Lout} PARAMETERS: LOUT = 75u COUT = 220u RLOAD = 10 Ga I(Lout) GVALUE

OUT+ OUT- IN+ IN-

Dbreak D1 VDon {VDon}

+

• c

PARAMETERS: RESR = 0.07 RINDUCTOR = 0.1 NODESET= 5

+

Cout {Cout} EDoff min(2*abs(I(Lout))*Lout/(Ts*(vin-V(a))*V(Don))-V(Don),1-V(Don)) etable

OUT+ OUT- IN+ IN-

PARAMETERS: VIN = 10v VDON = 0.5 Don Gb V(Don)*I(Lout)/(V(Don)+V(Doff)) GVALUE

OUT+ OUT- IN+ IN-

Resr {Resr} b Rinductor {Rinductor} Vexcitation 1V

+

• Vin_pulse

+

SLIDE 15

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 29]

RLoa d 10 20 30 40 50 60 70 80 90 100 V( Dof f ) 400mV 600mV 150mV SEL>> V( a ) / V( B) 400m 500m 600m 700m

Example: Buck DC Sweep Analysis (CCM/DCM)

LOAD

R ) in ( V )

• ut

( V

• ff

D DCM CCM

LOAD

R border line Don=0.5

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 30]

Example: Buck AC Analysis (CCM/DCM)

Fr e que nc y

• 1. 0Hz

10Hz 100Hz

• 1. 0KHz

10KHz 100KHz DB( V( a ) )

• 40
• 20

20 40

⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ) d ( v )

• ut

( v dB DCM : Rload=100 ohm CCM : Rload=10 ohm

SLIDE 16

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 31]

Buck AC Analysis (CCM/DCM) file .out

**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C **** CURRENT STEP PARAM RLOAD = 10 ****************************************************************************** NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( a) 4.5455 ( B) 10.0000 ( C)

• .8182 ( DON) .5000

( Doff) .5000 (N00069) -.0455 (N00141) 0.0000 (N000071) .5000 (N000230) 0.0000 VOLTAGE SOURCE CURRENTS NAME CURRENT V_Vexcitation 0.000E+00 V_VDon 0.000E+00 V_Vin -2.273E-01 **** CURRENT STEP PARAM RLOAD = 100 ****************************************************************************** NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( a) 6.9835 ( B) 10.0000 ( C) -.7340 ( DON) .5000 ( Doff) .1945 (N00069) -.0070 (N00141) 0.0000 (N000071) .5000 (N000230) 0.0000 VOLTAGE SOURCE CURRENTS NAME CURRENT V_Vexcitation 0.000E+00 V_VDon 0.000E+00 V_Vin -5.028E-02

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 32]

Rin Cf Rf Vref Ao

in f 2 f f L OL

• R

R A R C 2 1 f .) ampl ( A A = π = =

Lag Lead

SLIDE 17

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 33]

Exercise

f 200Hz 2kHz db 5 Ao = |A|

dec db

40 −

dec db

20 − Given Design β and feedback circuit for fel=5kHz

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 34]

f 200Hz 2kHz db 5 Ao = |A|

dec db

20 −

dec db

40 − 5kHz β 1 5db

• 35db

20 S 1 2 1 2 dec db dec db dec db dec db

f f A A 40 , 40 , 20 , 20 S ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − −

A1 A2 S f1 f2

Power Stage Example

SLIDE 18

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• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 35]

( )

db 5 . 42 5 . 7 35 A 5 2 lg 20 A A 5 2 A A 2 5 A A

db db db

2 1 2 1 1 2 1 2 1

− = − + = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ =

−

f 42.5db 1kHz 5kHz β kHz 1 RC 2 1 = π 2k 270k R C nF 59 . kHz 1 R 2 1 C = π =

Pole Zero

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 36]

Problem?

t AOL 30db 5kHz Operational amplifier limitation

SLIDE 19

19

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 37]

L

R

esr

R

• ut

C

• V
• ut

L

1

D MOD PWM

• n

D

V

ex

V D

in

V

puls in

V

Buck

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 38]

File: Buck_cy_by_cy.SCH

SLIDE 20

20

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 39]

Current Feedback

The problem: transfer function is

second order

Solution: Add current Feedback

System order is reduced for each state variable feedback

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 40]

AMP MOD k IL RL C D L S Vin

ε

V

e

V Vo

For strong feedback (AOL>>1):

) V ( V k 1 I

e L

→ =

ε

Current Feedback

SLIDE 21

21

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 41]

k Ve Co RL f

L e R

k V

L

• R

C 2 1 π

First order system !

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 42]

PCM & ACM

MOD Vo Vref Ve D inner loop

• uter loop

I L

IL/Ve flat

SLIDE 22

22

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 43]

Current mode (CM) control

! same the is ) D ( f V V

• n

in

• =

Driver FF Clock L R S Q IL fs Ve Inductor current IL

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 44]

Some controllers have amplifiers for sensed current Driver FF Clock L R comp S RS Cf Rf Vref Error AMP

Implementation CM Boost

SLIDE 23

23

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 45]

CM Controller

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 46]

Advantages of peak CM (PCM)

∗ Cycle by cycle protection ∗ Better dynamics

Disadvantages

∗ Loading edge spike ∗ Subharmonic oscillation

SLIDE 24

24

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 47]

The nature of Subharmonic Oscillations

The geometric explanation

L

I

L

I

1

I ∆

2

I ∆

2

I ∆

1

I ∆

e

V

e

V

S

T t t

D>0.5 ∆I2>∆I1 D<0.5 ∆I2<∆I1

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 48]

BOOST Average Model

Dbreak d1 Cf {Cf} sw PARAMETERS: KS = 81.25m TS = 40u MC = 6250 Red_c 1k Ed_c 1/(v(don)+v(doff)) etable

OUT+ OUT- IN+ IN-

Vin_DC {Vin_DC}

+

• Edon

fs*(v(Verror)-ks*i(vl)*v(d_c))/(mc+ks*(v(in)-v(sw))/(2*lin)) etable

OUT+ OUT- IN+ IN-

in PARAMETERS: RESR = 0.012 COUT = 2m VIN_DC = 28 rind 1m

• ut

R1 47.5k don Vexatation 1

+ -

d vl 0V

+

• rsw

{rsw}

• ut

vref 2.8

+

• cout

{cout} doff Redon 1k PARAMETERS: CF = 0.23u Rf 72.2k ref Gd i(vl)*v(d_c) gvalue

OUT+ OUT- IN+ IN-

Edoff min(abs((2*i(vl)*lin/(ts*v(don)*(v(in)-v(sw))))-v(don)),1-v(don)) etable

OUT+ OUT- IN+ IN-

Gdoff v(doff)*i(vl) gvalue

OUT+ OUT- IN+ IN-

d_c Gsw i(vl)*v(d_c) gvalue

OUT+ OUT- IN+ IN-

Vin_pulse

+

• Verror

ELs v(sw)*v(don)+(v(d)+v(out))*v(doff)+v(in)*(1-v(don)-v(doff)) evalue

OUT+ OUT- IN+ IN-

PARAMETERS: RSON = 1m RSW = {rson+rsen} RL = 11.2 VerrorLG Redoff 1k resr {resr} PARAMETERS: LIN = 195u RSEN = 0.025 FS = {1/ts} Evea V(%IN+, %IN-)*1e6 ETABLE

OUT+ OUT- IN+ IN-

RL {RL} R2 2.5k ref lin {lin}

AC analysis PCM (CCM & DCM)

SLIDE 25

25

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 49]

BOOST Average Model Simulation

Fr e que nc y

• 1. 0Hz
• 3. 0Hz

10Hz 30Hz 100Hz 300Hz

• 1. 0KHz
• 3. 0KHz

10KHz DB( V( out ) / V( Ve r r or LG) ) DB( V( out ) / V( Ve r r or ) )

• 30
• 20
• 10

10 20 30

β 1

OL

A

)) VerrorLG ( V / )

• ut

( V ( DB : 1 β )) Verror ( V / )

• ut

( V ( DB : AOL

Close loop Bandwidth

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 50]

BOOST Average Model Simulation

Fr e que nc y

• 1. 0Hz

10Hz 100Hz

• 1. 0KHz

10KHz 180+P( V( Ve r r or LG) ) - P( V( Ve r r or ) ) 180 200 90 360 DB( V( Ve r r or LG) / V( Ve r r or ) )

• 20

20 40 60 SEL>>

Loop Gain Phase Margin

730.5 kHz 252.6º 180º PM=252.6º-180º=72.6º PM

180 90 270 PM

OL

A β ∠

SLIDE 26

26

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 51]

Average Current Mode (ACM) Control

ref

V

• +
• +

fv

Z

inv

Z

fi

Z Vo PWM mod Current is filtered first to take out high frequency (fS)

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 52]

The advantages of current feedback (PCM or ACM)

f Gain

e

• v

v

dec db

40 −

dec db

20 −

Typical power stage VM

Gain

e

• v

v

dec db

40 −

dec db

20 −

Same power stage (outer loop) with CM

SLIDE 27

27

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 53]

Parasitic effects: PCB trace resistance

1 2

2 1

V V ≠

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 54]

Separate power ground from signal ground

PG G Vref Controller R1 Vcc R3 R2 "Ground Plane" VB CT

This circuit will probably not work. Why ?

Ground Noise

SLIDE 28

28

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 55]

Correct layout

G Vref Controller R1 Vcc R3 R2 "Ground Plane" VB CT

Do not rely on “Ground Plane”

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 56]

Schottky Diodes

SLIDE 29

29

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 57]

Parasitic effects: Interfering signal injection

Vref R1 R2 Sensitive Part-Capacitive coupling Stray capacitance

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 58]

Parasitic effects: Inductive coupling

R2 φ Do not put sensitive elements close to high voltage pulses or close to magnetic elements

SLIDE 30

30

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 59]

Avoid wide power line loops Stray inductance is proportional to area. So is the radiated wave.

Vin

l n A ~ L

2

µ

Current Loop Area

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 60]

Vin

Best way is to run the forward-return paths on two sides of the PCB

Loop Area

SLIDE 31

31

• Prof. S. Ben-Yaakov , DC-DC Converters

[10- 61]

Parasitic effects: Stray inductance

cm nH 1 Two points on power PCB trace will never have same potential

C B A

V V V ≠ ≠

Vin

B A C

Vin