[PPT] - An algorithmic Analog to Ditital Converter for CMOS image sensors PowerPoint Presentation

SLIDE 1

An algorithmic Analog to Ditital Converter for CMOS image sensors

Master’s Thesis Presentation Deyan Dimitrov

Link¨

ping University

June 12, 2013

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 2

Outline

Analog readout schemes in CMOS Image Sensors (CIS) General performance requirements from a column-parallel CIS ADC The Algorithmic/Cyclic ADC architecture A few explored MDAC configurations The Cyclic ADC implementation Designed ADC characterization and results Some improvement ideas Conclusion and possible future tasks

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 3

Introduction to image sensor readout

R O W D E C O D E R

ADC

Column Amplifiers/Sample and Hold Column Multiplexers

Basic serial readout

0101 0101 0101 0101 0101 0101 0101 0101 0101 0101

R O W D E C O D E R Local Memory and Drivers to on-chip processing

Basic parallel readout

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 4

A pixel (the device under read)

Main pixel parameters coupled to ADC requirements: Output range Integration (exposure) time Reset time Dark Noise PSRR A photogate-based active pixel

VDD p+ TX PG

Vreset Vword

n n

ut

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 5

Requirements over column-parallel CIS ADCs

Integral Non-Linearity - random uniform (8-bit image)

50 100 150 200 250 −15 −10 −5 5 10 15 Random uniform INL distribution. Code Dev in LSB

±1 LSB

50 100 150 200 250 −15 −10 −5 5 10 15 Random uniform INL distribution. Code Dev in LSB

±8 LSB

For visible spectrum, human eye starts recognizing distortion beyond 6-7% INL

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 6

Requirements over column-parallel CIS ADCs cont’d

Differential Non-Linearity - random single missing codes over the whole range (up-to 1 code from stair-to-stair)

Reference Image Random missing codes

Even if ±1 LSB, artifacts become visible to the eye.

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 7

Requirements over column-parallel CIS ADCs cont’d

Column ADC mismatch fixed-pattern noise effect (8-bit image), pattern used ∆rand1, ∆rand2, ∆rand3...

±2 LSB ±16 LSB

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 8

Requirements over column-parallel CIS ADCs cont’d

Full-scale step-response Out of range recovery Random noise Conversion speed: τconv <≈

1 Hfs

Nmencds − Nme τpixres + τpixsig 2 (1) Power consumption, typically: 100 ÷ 500 µW Resolution: 8 (very high speed imagers) ÷ 14 bits

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 9

The Algorithmic/Cyclic ADC architecture

Why cyclic?

Sub-AD φin

MDAC RSD [1 :0] WORDOUT [12 :0] vAnalogIn

φcycle

x2

analog input digitized analog signal residual signal

Sub-DA

partial result iteration loop

RSD to BIN Logic

A functional block diagram of a RSD Cyclic ADC

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 10

The Algorithmic/Cyclic ADC architecture cont’d

The RSD error correction scheme

”10” ”01” ”00” Vin Vin Vout Vout

ffset

clipped output Vref

1 4Vref 3 4Vref

ffset

”1” ”0”

nly offsets over 7

8 and below 1 8 will not be corrected

A comparative example between RSD and conventional ADC stages

Allows for Sub-AD comparator online offset error correction during each consecutive iteration (cycle)

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 11

A few explored MDAC configurations

Advantages/Disadvantages: ⊕ Offset cancellation ⊕ Parasitic insensitive ⊖ Amplifier BW limited ⊖ Matching dependent The ”flip-around” MDAC architecture

Cf Cs φ1 φ2 φ1 φ1 Vr(0, ±Vref) Vin Vout φ2 virtual ground Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 12

A few explored MDAC configurations cont’d

Advantages/Disadvantages: ⊕ Non-OP-BW limited (φ1) ⊕ Allows OP re-use at φ1 ⊖ No offset cancellation ⊖ Matching dependent The ”modified flip-around” MDAC architecture

Cf Cs φ1 φ2 φ1 Vr(0, ±Vref) Vin φ2 Vout φ1 φ1

More popular than the previous due to OP BW independence

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 13

A few explored MDAC configurations cont’d

The cap-stacking concept

2Vin q = CVin Vin Vin q = CVin Vin Cparasitic

An SC integrator - multiply by n structure

Vout Cf Cs φ1 φ1 φ2 φ2 Vin

Opamp high gain requirement Accumulates offset Parasitic sensitive

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 14

A few explored MDAC configurations cont’d

A MDAC with integrated analog CDS

C2 C5 C1 C3 C6 C4 Vref+ Vsig

Signal sampling

C2 C3 C6 Vref− C5 C1 C4 Vreset

Reset sampling

C1 C3 C6 C4 C2 C5 Vref+ Vref− φ3 φ4 within range to comparators to comparators

ver-range

under-range

Feedback and amplification

High complexity, non-trivial to design ”Bulky” design, multiple switches, phases, capacitors

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 15

Preliminary followed ADC design specifications

Parameter Value Unit Resolution 12 bits Sampling rate > 130 kSps Integral Non-Linearity < 10 LSB Differential Non-Linearity < 0.5 LSB Power consumption < 300 µW Supply voltage 3.3 ±10% V Process node 0.18 µm Area

µm

Main ADC specifications followed during the design study

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 16

The implemented Cyclic ADC

C1a Vcom C2 C1b VRH VRL Vcom φM φN φP φSD φ1D φINIT φ0 φS φ2 φ1 VIN to comparators

Principal schematic diagram of the cyclic core-architecture, as proposed by Jong-Ho Park et. al.

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 17

The implemented Cyclic ADC cont’d

OTA requirements DC Gain: > 84 dB ωug: > 10 MHz PSRR: > 40 dB Offset: ALAP Noise: < 200 µV 2 at BW range Power: 30 ÷ 50 µW Input and output ranges > pixel range Possible candidates Telescopic OTA Current mirror OTA Folded cascode OTA Two stage OTA

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 18

The implemented Cyclic ADC cont’d

VDD VDD VDD VDD

M8 M7 M12 M10 M1 M2 M3 M4 VINn Vout VINp CL Ibias 1 : B B : 1 M11 M5 M6 M9 Vbias Vbias Vbias Vbias

The implemented current mirror OTA architecture

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 19

The implemented Cyclic ADC cont’d

Comparator requirements Input offset: ± 1

8(VRH − VRL)

Response time: < 500 ns Resolution: > 400 µV Noise variance: < Input

ffset

Kickback noise: < left OTA recover time Power: < 10 µW Explored candidates Static latched comparator A Class AB latched comparator A fully dynamic latched comparator

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 20

The implemented Cyclic ADC cont’d

VDD VDD VDD VDD VDD VDD

Vlat M

′ 7

Vlat M

′′ 7

M

′ 1

M

′ 2

M

′′ 1

M

′′ 2

VPH VINp VPL VNL VOP H M

′ 3

Vlat Vlat M

′′ 4

M

′′ 6

M

′′ 8

Vlat Vlat VONL M

′′′ 3

M

′′′ 5

M

′′′ 6

M

′′′ 8

M

′′′ 11

M

′′′ 10

Vlat Vlat M

′′′ 4

M

′ 4

M

′ 10

M

′ 8

M

′ 5

M

′ 6

M

′ 9

M

′ 11

M

′′ 3

M

′′ 10

M

′′ 5

M

′′ 9

M

′′ 11

M

′′′ 9

VONH VOP L VOP M VONM

A principal schematic diagram of the implemented Sub-AD comparators

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 21

The implemented Cyclic ADC cont’d

Switch requirements Input range: VRL ÷ VRH + margin Ron: to achieve a reasonable settling-time Charge injection: at MSB cycle < VLSB distortion Explored candidates Clock-boosted techniques A Bootstrapped switch technique A transmission-gate based switch

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 22

The implemented Cyclic ADC cont’d

∆ C1a Vcom C2 C1b VRH VRL Vcom φM φN φP φSD φ1D φINIT φ0 φS φ2 φ1 VIN to comparators LA LA LA ∆ φ1 φ1D φ2

Vgp Vgn Vin holes electrons Vout

A clarification of the considered accuracy-critical switch nodes

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 23

Some improvement ideas

Two capacitor mismatch effect reduction techniques: Even-odd fashion cap flipping

σmm = C1 C2 − 1 (2) σgainp,n = G ± Gσmm (3) Sflipping =

i=1≤k≤i,odd

1 2k σgainp +

(4)

i=1≤k≤i,even

1 2k σgainn

(5) Snon−flipping =

k

1

1 2k σgainp

(6)

Capacitor flipping switch network changes for the current MDAC

C1a C1b Vcom Vcom φ2 φ1 C2a C2b φf φf φs φs φs φs φf φf φf φf φs φs φs φs φf φf DAC

Cap flipping MDAC modifications

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 24

Some improvement ideas cont’d

Pseudo cap-flipping Flip caps once after MSB has been resolved (cycle 1)

Spc = 1 2 σgainx +

i=2≤k≤i

1 2k σgainy (7) σredpc =

Spc

Snon−pc − 1

.100

(8)

Capacitor flipping switch network changes for the current MDAC

Error reduction, [%] Converter resolution/cycles, bits 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0 2 4 6 8 10 12 14 16 with pseudo-calibration even-odd basis cap flipping

A comparative error reduction progress between the even-odd capacitor flipping technique and the proposed pseudo-calibration flipping method. C1=500 fF, C2=487 fF Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 25

Designed ADC characterization and results

Static linearity tests (no capacitor mismatch) INL

Dev in LSB 1.5 1 0.5 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 Code 500 1000 1500 2000 2500 3000 3500 4000 4500

Simulated Integral Non-Linearity, worst case process corner, 3V3, 70 ℃, transient noise included

DNL

Dev in LSB Code 1 0.8 0.6 0.4 0.2 −0.2 −0.4 −0.6 −0.8 −1 500 1000 1500 2000 2500 3000 3500 4000 4500

Simulated Differential Non-Linearity, worst case process corner, 3V3, 70 ℃, transient noise included Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 26

Designed ADC characterization and results cont’d

Summarized results

Parameter Value Unit Technology UMC 0.18µm G-02-MIXED MODE/RFCMOS18- 1.8V/3.3V-1P6M

Resolution

12 bits Sampling Rate < 150 kSps Input Voltage Range 1.35 (1 ÷ 2.35) V Integral Non-Linearity 1 +1.5/-3.5 LSB Differential Non-Linearity 2 ±0.8 LSB Random Noise 3 367 µV Power Supply, TYP 3.3 V Power Consumption core @ 3V3, 70 ℃, TYP 72 µW Power Consumption core+logic @ 3V3, 70 ℃, TYP 193 µW Energy per Conversion Cycle @ 3V3, 70 ℃, TYP 15.4 µJ Reference Voltage H 2.35 V Reference Voltage L 1.00 V 1Integral Non-Linearity measured without capacitor mismatch at worst case corner 2Differential Non-Linearity measured without capacitor mismatch at worst case corner 3Based on a 1500 sample transient noise (5 Hz - 200 MHz) runs, measured in the middle of the input range Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 27

Conclusion and possible future tasks

An analysis on the architectural choice was performed, all basic ADC core component requirements were identified. A few MDAC architectures have been explored and a choice, transistor-level design and verification was conducted. Three comparator architectures were explored, a comparative analysis between the latter was performed. A transistor-level Sub-ADC was designed. Two capacitor mismatch error improvement schemes were explored.

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

SLIDE 28

Conclusion and possible future tasks cont’d

More component optimization and verification has to be done

design is by far not tape-out ready.

No parasitic estimations have been made. Layout and post-layout verification is necessary after settling. An RTZ coding signal feedback may be a relevant feature to implement, with this SE MDAC design. It may be wiser to change the Sub-ADC interpolative architecture. Capacitor flipping schemes appear very relevant to investigate for this application. Simplified digital background calibration schemes are worth checking-out.

Deyan Dimitrov Link¨

ping University

An algorithmic Analog to Ditital Converter for CMOS image sensors