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VHDL Syntheses Subset 1 Combinational Logic Simple Signal - PowerPoint PPT Presentation

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VHDL Syntheses Subset 1 Combinational Logic Simple Signal Assignment Conditional Signal Assignment Selected Signal Assignment Relational and Arithmetic Operators(excp DIV/MODE/**) Three State LOOP,CASE,IF 2 General

  1. VHDL Syntheses Subset 1

  2. Combinational Logic • Simple Signal Assignment • Conditional Signal Assignment • Selected Signal Assignment • Relational and Arithmetic Operators(excp DIV/MODE/**) • Three State • LOOP,CASE,IF 2

  3. General Style Process(rhs signals) variable declarations Begin a<=“000”; if(v=‘1’) then z:=a; y<=b; elsif a<=“0101”; end if; End process; 3

  4. Sequential Logic • Using edge detection and IF statement within Process 4

  5. Asynchronous Set/Reset Process(clk,set,reset) Begin if(set=‘1’) then stmt1; elsif(reset=‘1’) then stmt2; elsif(clk’event and clk=‘1’) then stmt3; end if; End process; 5

  6. Synchronous Set/Reset Process(clk,set,reset) Begin If(clk’event and clk=‘1’) then if(set=‘1’) then stmt1; elsif(reset=‘1’) then stmt2; else stmt3; end if; End if; End process; 6

  7. Synchronous with enable Process(clk,set,reset) Begin If(clk’event and clk=‘1’) then if(Enable=‘1’) then stmt1; end if; End if; End process; 7

  8. Counters Process(clk,set,reset) Begin If(clk’event and clk=‘1’) then Counter<=Counter+1; End if; End process; 8

  9. State Machines Process(clk) Begin If(reset=‘1’) CurrentState<=st1; elsIf(clk’event and clk=‘1’) then Case CurrentState IS when st1=> if(input=val1) next_state;=st3; end if; when st2=> if(input=val2) next_state:=st1; end if when st3=> if(input=val1) next_state:=st2; end if when others=> next_state:=st1; End case; End if; CurentState<=next_state; If(CurrentState=st2) then z<=‘1’ end if; End process; 9

  10. Chapter 10 Parwan Dataflow Model 10

  11. Dataflow Model DBUS Memory Memory DATABUS AR OFFSET AR PAGE AC PC PAGE PC OFFSET IR Alu Alu DBUS Controller Controller SHU SHU MAR BUS StR AR_PAGE AR_OFFSET ADBUS OBUS 11

  12. In/Out of Parwan Controller Applies To Category Signal Name AC REG load_ac,zero_ac IR REG load_ir MAR REG load_page_mar,load_offset_mar SR REG load_sr,cm_carry_sr PC REG increment_pc,load_page_pc,load_offset_pc,reset_pc MAR_BUS BUS pc_on_mar_page_bus, ir_on_mar_page_bus, pc_on_mar_offset_bus, ir_on_mar_offset_bus DBUS BUS pc_offset_on_dbus,obus_on_dbus,databus_on_dbus ADBUS BUS mar_on_adbus DATABUS BUS dbus_on_databus SHU LOGIC arith_shift_left, Arith_shift_right, ALU LOGIC alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub OTHERS I/O read_mem,write_mem,interrupt 12

  13. ALU description ENTITY alu IS PORT (a_side,b_side:IN byte; alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub : IN qit; flags_in : IN nibble; flag_out: OUT nibble; z: OUT byte ); 13

  14. ALU description ARCHITECTURE behavioral OF alu IS BEGIN Coding:PROCESS( alu_and,alu_not,alu_a,alu_add,alu_b,a lu_sub,flag_in,a_side,b_side) VARIABLE t:qit_vector( 9 downto 0); VARIABLE v,c,n,z:qit; ALIAS n_flag_in: qit IS in_flag(0); ALIAS z_flag_in: qit IS in_flag(1); ALIAS c_flag_in: qit IS in_flag(2); ALIAS v_flag_in: qit IS in_flag(3); 14

  15. ALU description BEGIN CASE qit_vector(5 downto 0)’(alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub) IS WHEN a_add_b => t:=add_cv(b_side,a_side,c_flag_in); c:=t(8); v:=t(9); WHEN a_sub_b => t:=sub_cv(b_side,a_side,c_flag_in); c:=t(8); v:=t(9); WHEN a_and_b => t(7 downto 0):=b_side AND a_side; c:=c_flag_in; v:=v_flag_in; WHEN a_input => t(7 downto 0):=a_side; c:=c_flag_in; v:=v_flag_in; 15

  16. ALU description WHEN b_input => t(7 downto 0):=b_side; c:=c_flag_in; v:=v_flag_in; WHEN b_compl => t(7 downto 0):=NOT b_side; c:=c_flag_in; v:=v_flag_in; WHEN OTHERS => NULL: END CASE; n:=t(7); Z:=set_if_zero(t(7 downto 0)); Out_flag<=(v,c,z,n); END PROCESS codeing; END behavioral; 16

  17. Shifter Unit ENTITY Sifter_unit IS PORT( alu_side: IN byte; arith_shift_left,arith_shift_right: in qit; flag_in: nibble; flag_out:nibble; obus_side: byte ); 17

  18. Shifter Unit ARCHITECTURE behavioral of shifter_unit is BEGIN Codeing:PROCESS(alu_side,arith_shift_left ,arith_shift_right) VARIABLE t:qit_vector( 7 downto 0); VARIABLE v,c,n,z:qit; ALIAS n_flag_in: qit IS in_flag(0); ALIAS z_flag_in: qit IS in_flag(1); ALIAS c_flag_in: qit IS in_flag(2); ALIAS v_flag_in: qit IS in_flag(3); 18

  19. Shifter Unit BEGIN IF( arith_shift_left=‘0’ AND arith_shift_right=‘0’) then t:=alu_side(7 downto 0); (v,c,z,n):=flag_in; ELSIF(arith_shift_left=‘1’ ) then t:=alu_side(6 downto 0) & ‘0’; n:=t(7); z:=set_if_zero(t); c:=alu_side(7); v:=alu_side(6) XOR alu_side(7); 19

  20. Shifter Unit ELSIF(arith_shift_right=‘1’ ) then t:= alu_side(7) & alu_side(6 downto 0); n:=t(7); z:=set_if_zero(t); c:=c_flag_in; v:=v_flag_in; END IF; obus<=t; flag_out<=(v,c,z,n); END PROCESS; END; 20

  21. Status Register ENTITY sr IS PORT( in_flags: IN nibble; out_flags: OUT nibble; load,cm_carry,ck: IN qit ); END; 21

  22. Status Register ARCHITECTURE behavioral OF sr IS BEGIN PROCESS(ck) variable internal_state:nibble:=“0000”; alias internal_c:qit is internal_state(2); BEGIN if( ck=‘0’) then if(load=‘1’) then internal_state:=in_flags; end if; elsif(cm_carry=‘1’) then internal_c:=NOT internal_c; end if; out_status<=internal_state; END PROCESS; END; 22

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