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2
Combinational Logic
- Simple Signal Assignment
- Conditional Signal Assignment
- Selected Signal Assignment
- Relational and Arithmetic Operators(excp
DIV/MODE/**)
- Three State
- LOOP,CASE,IF
VHDL Syntheses Subset 1 Combinational Logic Simple Signal - - PowerPoint PPT Presentation
VHDL Syntheses Subset 1 Combinational Logic Simple Signal - - PowerPoint PPT Presentation
VHDL Syntheses Subset 1 Combinational Logic Simple Signal Assignment Conditional Signal Assignment Selected Signal Assignment Relational and Arithmetic Operators(excp DIV/MODE/**) Three State LOOP,CASE,IF 2 General
SLIDE 2
SLIDE 3
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General Style
Process(rhs signals) variable declarations Begin a<=“000”; if(v=‘1’) then z:=a; y<=b; elsif a<=“0101”; end if; End process;
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Sequential Logic
- Using edge detection and IF statement
within Process
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Asynchronous Set/Reset
Process(clk,set,reset) Begin if(set=‘1’) then stmt1; elsif(reset=‘1’) then stmt2; elsif(clk’event and clk=‘1’) then stmt3; end if; End process;
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Synchronous Set/Reset
Process(clk,set,reset) Begin If(clk’event and clk=‘1’) then if(set=‘1’) then stmt1; elsif(reset=‘1’) then stmt2; else stmt3; end if; End if; End process;
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Synchronous with enable
Process(clk,set,reset) Begin If(clk’event and clk=‘1’) then if(Enable=‘1’) then stmt1; end if; End if; End process;
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Counters
Process(clk,set,reset) Begin If(clk’event and clk=‘1’) then Counter<=Counter+1; End if; End process;
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State Machines
Process(clk) Begin If(reset=‘1’) CurrentState<=st1; elsIf(clk’event and clk=‘1’) then Case CurrentState IS when st1=> if(input=val1) next_state;=st3; end if; when st2=> if(input=val2) next_state:=st1; end if when st3=> if(input=val1) next_state:=st2; end if when others=> next_state:=st1; End case; End if; CurentState<=next_state; If(CurrentState=st2) then z<=‘1’ end if; End process;
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Chapter 10
Parwan Dataflow Model
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Dataflow Model
Controller Controller Memory Memory AC SHU SHU Alu Alu
PC OFFSET PC PAGE
IR
AR_PAGE AR_OFFSET
StR
DBUS OBUS ADBUS
DBUS AR PAGE AR OFFSET DATABUS MAR BUS
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In/Out of Parwan Controller
read_mem,write_mem,interrupt I/O OTHERS alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub LOGIC ALU arith_shift_left, Arith_shift_right, LOGIC SHU dbus_on_databus BUS DATABUS mar_on_adbus BUS ADBUS pc_offset_on_dbus,obus_on_dbus,databus_on_dbus BUS DBUS pc_on_mar_page_bus, ir_on_mar_page_bus, pc_on_mar_offset_bus, ir_on_mar_offset_bus BUS MAR_BUS increment_pc,load_page_pc,load_offset_pc,reset_pc REG PC load_sr,cm_carry_sr REG SR load_page_mar,load_offset_mar REG MAR load_ir REG IR load_ac,zero_ac REG AC Signal Name Category Applies To
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ALU description
ENTITY alu IS PORT (a_side,b_side:IN byte;
alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub : IN qit; flags_in : IN nibble; flag_out: OUT nibble; z: OUT byte
);
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ALU description
ARCHITECTURE behavioral OF alu IS BEGIN Coding:PROCESS(alu_and,alu_not,alu_a,alu_add,alu_b,a
lu_sub,flag_in,a_side,b_side) VARIABLE t:qit_vector( 9 downto 0); VARIABLE v,c,n,z:qit; ALIAS n_flag_in: qit IS in_flag(0); ALIAS z_flag_in: qit IS in_flag(1); ALIAS c_flag_in: qit IS in_flag(2); ALIAS v_flag_in: qit IS in_flag(3);
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ALU description
BEGIN
CASE qit_vector(5 downto 0)’(alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub) IS WHEN a_add_b => t:=add_cv(b_side,a_side,c_flag_in); c:=t(8); v:=t(9); WHEN a_sub_b => t:=sub_cv(b_side,a_side,c_flag_in); c:=t(8); v:=t(9); WHEN a_and_b => t(7 downto 0):=b_side AND a_side; c:=c_flag_in; v:=v_flag_in; WHEN a_input => t(7 downto 0):=a_side; c:=c_flag_in; v:=v_flag_in;
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ALU description
WHEN b_input => t(7 downto 0):=b_side; c:=c_flag_in; v:=v_flag_in; WHEN b_compl => t(7 downto 0):=NOT b_side; c:=c_flag_in; v:=v_flag_in; WHEN OTHERS => NULL:
END CASE; n:=t(7); Z:=set_if_zero(t(7 downto 0)); Out_flag<=(v,c,z,n); END PROCESS codeing; END behavioral;
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Shifter Unit
ENTITY Sifter_unit IS PORT( alu_side: IN byte; arith_shift_left,arith_shift_right: in qit; flag_in: nibble; flag_out:nibble;
- bus_side: byte
);
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Shifter Unit
ARCHITECTURE behavioral of shifter_unit is BEGIN
Codeing:PROCESS(alu_side,arith_shift_left ,arith_shift_right)
VARIABLE t:qit_vector( 7 downto 0); VARIABLE v,c,n,z:qit; ALIAS n_flag_in: qit IS in_flag(0); ALIAS z_flag_in: qit IS in_flag(1); ALIAS c_flag_in: qit IS in_flag(2); ALIAS v_flag_in: qit IS in_flag(3);
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Shifter Unit
BEGIN IF(arith_shift_left=‘0’ AND arith_shift_right=‘0’) then
t:=alu_side(7 downto 0); (v,c,z,n):=flag_in; ELSIF(arith_shift_left=‘1’ ) then t:=alu_side(6 downto 0) & ‘0’; n:=t(7); z:=set_if_zero(t); c:=alu_side(7); v:=alu_side(6) XOR alu_side(7);
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Shifter Unit
ELSIF(arith_shift_right=‘1’ ) then t:= alu_side(7) & alu_side(6 downto 0); n:=t(7); z:=set_if_zero(t); c:=c_flag_in; v:=v_flag_in;
END IF;
- bus<=t;
flag_out<=(v,c,z,n); END PROCESS; END;
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Status Register
ENTITY sr IS PORT( in_flags: IN nibble;
- ut_flags: OUT nibble;
load,cm_carry,ck: IN qit ); END;
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Status Register
ARCHITECTURE behavioral OF sr IS BEGIN PROCESS(ck) variable internal_state:nibble:=“0000”; alias internal_c:qit is internal_state(2); BEGIN if( ck=‘0’) then if(load=‘1’) then internal_state:=in_flags; end if; elsif(cm_carry=‘1’) then internal_c:=NOT internal_c; end if;
- ut_status<=internal_state;
END PROCESS; END;