Update on the Si-Strip Tests Hans-Georg Zaunick HISKP Universitt - PowerPoint PPT Presentation

1 Update on the Si-Strip Tests Hans-Georg Zaunick HISKP Universität Bonn PANDA collaboration meeting, GSI, March 3, 2008 HG Zaunick Update on the Si-Strip Tests

2 Si-Strip test station in Dresden PC I 2 C- slow control USB USB Master I 2 C (FX2) Teststation L-Board I 2 C ● slow control Clk v1.4 Supply • APV register Trig Clock/ Clk • set voltage _____________________ _____________________ _____________________ Board Trigger _____________________ _____________________ • monitor _____________________ _____________________ _____________________ Data _____________________ _____________________ Trig sensor _____________________ _____________________ APV _____________________ _____________________ _____________________ Control currents _____________________ _____________________ v1.2 _____________________ _____________________ LVDS _____________________ _____________________ _____________________ LVDS _____________________ _____________________ (Spartan) ● clock/trigger _____________________ _____________________ _____________________ _____________________ _____________________ Power _____________________ _____________________ control Clk Trig LVDS • set clock Power Data LVDS • set trigger parameter signal • send trigger conversion • calibration differential HV ● DAQ receiver Clk Trig SE • scans Data • spectra Gage • histos SE PCI ADC card LVDS low voltage differential signal RS232 SE single ended CMOS HG Zaunick Update on the Si-Strip Tests

3 Sensor-PCB L-shape for double sided mounting mechanical support for sensor/pitch adaptor/FEs supply/bias voltage distribution HG Zaunick Update on the Si-Strip Tests

4 Low Level Feature Exraction Framework light weight framework set up for current data structures merged Dresden/Bonn low level hit/cluster processing+reco merged with PANDARoot but may be also used stand alone SVN Repository Checkout feel free to use/contribute, please contact me for checkout HG Zaunick Update on the Si-Strip Tests

5 Clustering comparison of different clustering L. Ackermann (Dresden) algorithms resolution dependent on cluster sizes 1 incident angle 2 algorithm 3 d p θ HG Zaunick Update on the Si-Strip Tests

6 Module Parameter MySQL Database DB containing information about all characterized Modules set up by F . Krüger (Dresden) HG Zaunick Update on the Si-Strip Tests

7 Lab setup in Bonn Implementation of VME-based R/O high modularity → ease of table top setups HG Zaunick Update on the Si-Strip Tests

8 Feature Extraction and data Sparsification implemented in FPGA first tests running with 10MHz R/O clock fast ADCs with up to 65 MSPS coming soon... HG Zaunick Update on the Si-Strip Tests

9 Fast-ADC Mezzanine Card for VME-FPGA R/O card (custom CB-Module) submission this week R.Schnell (Dresden) HG Zaunick Update on the Si-Strip Tests

10 Tracking Station goals: resolution studies at Si-Sensors measurement of multiple scattering for various materials/configurations for MVD case HG Zaunick Update on the Si-Strip Tests

11 ELSA beam setup for TPC Testbench HG Zaunick Update on the Si-Strip Tests

12 HG Zaunick Update on the Si-Strip Tests

13 Conclusion evaluation of fully mounted modules w/ double sided readout has begun set up of DB for characterisations of prototype modules and to get familiar with QA processes modular construction of Si-Strip-Sensor “building blocks” HG Zaunick Update on the Si-Strip Tests

14 Whats next? tracking station to study "real life" track resolution and multiple scattering in compound material samples (for MVD-Mec), will be done by two Diploma Students in Bonn (M.Becker, K.Koop) Integration of Strip-FEE readout into Jülich MVD-R/O-Framework HG Zaunick Update on the Si-Strip Tests

15 Announcement PANDA-FE-DAQ Workshop Bavarian Forest, April 22-24 (Organisers: I. Konorov, W. Kühn) all subdetector groups should introduce their requirements on FE-DAQ interface (bandwidth, format, link types, synchronization etc.) discussion of common issues like global clock, compute nodes etc. Online Detector Data Processing - Algorithms, implementations, hardware requirements informations will be collected and made available online more information can be found at: http://www.e18.physik.tu- muenchen.de/research/panda/FEDAQmeeting09.html HG Zaunick Update on the Si-Strip Tests