Thin pixel assembly fabrication development with backside - - PowerPoint PPT Presentation

Thin pixel assembly fabrication development with backside compensation layer

• R. Bates1, C. Buttar1, T. McMullen1, G. Pares2, L. Vignoud2,
• 1. Experimental Particle Physics Group, University of Glasgow,

UK G12 8QQ

• 2. CEA Léti – MINATEC, 17 rue des Martyrs ; F-38054

GRENOBLE - France On behalf of the UK ATLAS Pixel upgrade groups

• Motivation for thin hybrid modules

– Material via worked examples – Through silicon vias

• Manufacture of hybrid module
• Issues with thin chip processing

– Existing technology for ATLAS IBL process

• Backside dielectric layer bow compensation

– Technical motivation – Run though the process – First results

Contents

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• Reduced mass of vertex/tracking

systems

• Interconnect through the readout

circuit

– Through silicon vias

Motivation for thin hybrid modules

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All-silicon inner detector (strips + expanded pixel system)

ATLAS Phase-II Tracker Upgrade

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Baseline LoI layout of the new ATLAS inner tracker for HL-LHC Aim to have at least 14 silicon hits everywhere (robust tracking)

Forward ¡pixel ¡ Long ¡Barrel ¡Strips ¡ Short ¡Barrel ¡Strips ¡ Forward ¡Strips ¡ Barrel ¡pixel ¡ Occupancy for <µ>=200 (in %)

ATLAS Letter of Intent CERN-2012-022 LHCC-I-023

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All-silicon inner detector (strips + expanded pixel system)

ATLAS Phase-II Tracker Upgrade

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Baseline LoI layout of the new ATLAS inner tracker for HL-LHC Aim to have at least 14 silicon hits everywhere (robust tracking)

Forward ¡pixel ¡ Long ¡Barrel ¡Strips ¡ Short ¡Barrel ¡Strips ¡ Forward ¡Strips ¡ Barrel ¡pixel ¡ Occupancy for <µ>=200 (in %)

ATLAS Letter of Intent CERN-2012-022 LHCC-I-023

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Phase-II pixel system in numbers

Inner radii: 2 layers

Layer 1: 352 2-chip modules Layer 2: 576 4-chip modules Issues: radiation damage & small pixels 1.4x1016n/cm2; 7.7MGy Forward pixels 16 rings per side 1680 4-chip modules Issues: large scale production of cheap thinned modules 1.8x1015n/cm2; 0.9MGy

Outer radii: 2 layers

Layer 3 & 4: 2940 4-chip modules Issues: large scale production of cheap thinned modules 1.7x1015n/cm2; 0.9MGy

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7.8m2 of Silicon hybrid pixel modules

Outer radii pixel system

• Pixel modules should be

– Large with high active fraction – Small contribution to material budget – Radiation tolerant – Highly granular – Optimised for production

• 2 outer Barrel layers & Disks

– Sensor planar n-in-p – Match to FE-I4 geometry ~2x2cm2 – Pixel size 50 µm x 250 µm – 2x2 FE-I4 (Quad) ~4x4cm2 – Aim for sensor & ROIC thickness ~150 µm each Current ATLAS Phase-II upgrade ATLAS

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• 200um ROIC, 300um sensor
• Ti Pipe

– OD 2.275mm / ID 2.000mm

• Carbon foam supports

– 4.6mm carbon foam (0.36gcm-3) – 0.13mm CFRP facings on both sides (FAW=100gcm-2)

• Silicon = 30% of ring!

Material and Si Module fraction

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Total = 2.02% X0

module silicon module other cables and tabs EOS card structure

Material of a ring

0% 1% 2% 3% 4% 5% 6% 7% 8% 9% 10%

1.74 1.82 1.9 1.98 2.06 2.14 2.22 2.3 2.38 2.46 2.54 2.62 2.7 2.78 2.86 2.94 3.02 3.1 3.18 3.26 3.34 3.42 3.5 3.58 Fraction of a Radiation Length Pseudo-rapidity

Front End Plate Rear End Plate Outer Cylinder Middle Cylinder Inner Cylinder Outer Rings Middle Rings Inner Rings

• Single point resolution ≈ 3-5 µm

– Vertexing & momentum measurement

• 0.2% X0/layer including supports
• Air cooled
• Hybrid Pixel module:

– Fully depleted : Time slicing (~ 10ns) for background reduction – Fast sparsified read-out – High single point resolution (3µm) : 20x20 µm2 pixel sizes

• CLICpix 50um thick ROIC and 50um thick sensor

CLIC Vertex detector material

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Single point resolution Multiple scattering term

• TSVs connect readout chips to the PCB: easy to tile chips on all 4 sides, fill

factor close to 100%.

– Distributed periphery removes EOCL dead area

• TSV

– Almost negligible inductance -> good for fast digital signals – Resistance: <100mOhm/TSV (20mOhm with wirebonds)

• Many contacts distributed across the chip à much smaller chip IR drop.
• TSV last process preferred

– Removes requirement on CMOS vendor

• High aspect ratio (5:1) vertical side wall TSV

Through Silicon Vias (TSV) advantages

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TSV options

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Via 40 µm OD -> 120 µm substratee

Process stages for 2.5/3D chip stacking

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u TSV Last u Interconnections u Under Bump Metallurgy (UBM) u Redistribution layer (RDL) u Stacking AR 1:1 AR 2:1 AR 3:1

Combine technologies for greater functionality

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Solder bumps TSV TSV and micro-bump stack detail

Bump deposition process

• 1. Wafer cleaned & inspected
• 2. TiW/Cu seed layer for UBM
• 3. Photolithography
• 4. Electroplating Cu (Ni) UBM/Pillar
• 5. Solder deposited on top of UBM

1. Different alloys available

• 6. Photoresist stripped
• 7. Seed layers wet etched away
• 8. Bump formed and isolated
• 9. Solder reflow– a flux-free process

1. Solder reflow done in reducing gas ambient

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Solder bumping using electroplating in a single mask processes

• Different bump structures possible:

– Structure #1: ROIC: Cu/SnAg – Sensor: thin film UBM – Structure #2: ROIC: Ni/SnPb – Sensor: Ni/SnPb

Flip-chip process

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Structure #2 solder bumps structure and assembly sequence Structure #1, Cu/SnAg pillars bonded against Pt UBM 240C

Room Temperature Indium bump bonding

• Indium bump bonding can be done at

room temperature

– Avoids issues with ROIC bowing

• Process:

– Thick photoresist – Cr UBM process – thermal evaporation – Indium deposition – thermal evaporation – Lift-Off – Flip-chip

• 99.9% Electrical yield

– Daisy chain test structures

• Produced first FE-I4 module
• Good bond yield (>99%) with a few

shorts

22micron ¡bumps ¡grown ¡ using ¡evaporator ¡and ¡ formed ¡using ¡reflow ¡oven ¡ at ¡RAL ¡

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Simply process thin wafer and flip-chip

• Evaluated bond yield of

thinned single chip module

– Use noise and cross-talk measurements

• Large areas of non-bonded

pixels at the corners & edges

– Have 3% to 66% open bumps

• 100% Yield for full

thickness devices

Bump Process Flow 1. Deposit UBM and bumps on ROIC 2. Thin ROIC to 200 µm / Diced 3. On vacuum jigs perform flip-chip for tack bond to sensor 4. Re-flow in reducing atmosphere in

• ven (240C) unsupported

assembly

Self-align bumps Obtain good electrical properties

Issues with bump yield due to significant bowing of large readout chip

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Bow on thin die

• FE-I4B die
• Silicon thickness = 100 µm
• Annealed after CMP
• TDM data
• Bow of die results in low Sn solder bumped

assembly yield due to high re-flow temperature

RT 260C

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Calculation of bow

• Simple bi-metallic calculation for

uniform thin film layer (<5% substrate thickness)

• Stoney’s Equation for film stress
• From CTE miss-match
• Keep ΔT small for ts thin
• 1µm thick AlSi deposited on

a bare Si wafer at 750µm

• Good linear behavior during

thermal cycle

• Modulus (from

nanoindentation) = 45 Gpa

• CTE is estimated ~ 18 ppm

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σ f = Es 6R ts

2

t f

σ f = E f α f −αs

( )ΔT

B = 3 4 ΔTt f ts

2

L2E fΔα Es

• 20
• 16
• 12
• 8
• 4

4 8 12 16 20 24 28 32 50 100 150 200 250 300

Warpage (µm) Temperature (C) Well modeled

More complex ROICs

• Die has many layers with

different mask densities

– Also film thickness 16% of substrate

• Model can be extended to

cover many layers with differing mask densities

– But need to know details

• For n layers with γ%

coverage per layer

• With lack of knowledge

eventually measure die bow

• Model effect of extra well

characterized deposited layers

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20 ∼16µm SEM x-section of FE chip showing the full front-side CMOS stack and differing metal densities through the layers

Btot = 3L2 4 E f (i)α f (i)t f (i)ΔTf (i) Ests

2

" # $ % & '

i=1 n

∑

γ f (i)

FE-I4B 100 µm thick with no stress compensation

25C 260C 260C 260C 25C 200 µm 20 µm

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• 200
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• 150
• 125
• 100
• 75
• 50
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25 50 75 100 125 20 40 60 80 100 120 140 160 180 200 220 240 260 280

Bare Die Warpage (µm) Temperature (C) Start

TDM Measurements of 100µm thick FEI4B Die thermally cycled 3 times RT to 260C

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Non-linear deformation with temperature Bow sign change with increasing temperature

How to live with bow issue

• Temporary bond thinned

ROIC (150 µm) to thick glass support wafer

• Process wafer and flip-

chip

• Laser Release support

wafer

• Used for IBL

– <300 modules

• Limitations

– speed & cost of processes – Heat, laser/UV glue removal, melts bumps with very thin ROIC

• No open bonds

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Glass support wafer 90 µm ROIC

Backside layer compensates bow

Incoming Wafer Temporary bonding Front-side processing – bump deposition Backside processing Backside Compensation Debonding onto tape and delivery to Flip-chip

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Leti Stress compensation

Objective : Max bow < 20 µm of interposer die between 20 & 260°C

• Basic characterization of thin

film material:

– CTE measurement vs temperature with RX diffraction (high sensitivity and accuracy method) – Young modulus extraction with nano- indention method

• Work at wafer level:

measurement and modeling of bow evolution with temperature with stacked deposition layers

• Work at die level: Topography

and Deformation Measurement (TDM) to vaildate the behavior of die bow with temperature

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25 Mesure de CTE=f(T°C) TDM of polymer layer on 80 µm Si interposer Modeling vs experiment

• 5.5mm bow after front-side

processing on a 50um thick wafer

• Wafer pulled flat after

backside compensation applied

CEA-LETI Interposer with backside compensation

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FE-I4B 100 µm thick with SiN/AlSi compensation

25C 260C 260C 260C 25C Corners might be due to single die deposition Need wafer level deposition to understand 200 µm 20 µm

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• 200
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• 150
• 125
• 100
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25 50 75 100 125 20 40 60 80 100 120 140 160 180 200 220 240 260 280

2µm SiN / 5µm AlS 0.5µm SiN / 4µm AlSi Bare Die

• Warpage amplitude greatly reduced by

almost 3x

• Note the complete sign change of the

warpage at ambient temperature

• Ambient temperature and gradient of the

warpage is thought to be manipulated by deposition conditions of the backside compensations stack

Warpage (µm) Temperature (C) Start Start Start

TDM Measurements of 100µm thick FEI4B Die thermally cycled 3 times RT to 260C

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• Ambient bow over compensated
• Change in bow = 80 µm for ΔT=235C
• Corners still bend up

– Likely to be due to single die processing – Corners not well clamped during deposition -> different temps – Run on full wafer under way

Best result so far

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• 200
• 180
• 160
• 140
• 120
• 100
• 80
• 60
• 40
• 20

50 100 150 200 250 300

Warpage max (µm) Temperature (°C)

SiN0.5µm/AlSi 4 µm as above but Ti 20 nm between the SiN and AlSi

Near future plans

• Results did not agree totally with model

– Predicted bow sign change – Model gave similar change in bow due to temperature change – But ambient temperature bow offset not well modeled

• Backside deposition temperature affects bow
• Single die processing not well suited for corners
• Move to wafer level to gain further insight into process
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• Thin hybrid pixel modules desirable
• Less material
• TSV enabling
• Initial back side stack shows promising results to compensate for the

CMOS front-side CTE mismatch on chips with a 100µm thickness

• Development still under way
• Backside stack starting bow and thermal cycle gradient is believed to

be tuneable by the deposition conditions

• Back-side compensation is good for production:
• Wafer level approach
• Less expensive than single module mechanical approach
• Higher throughput
• Back-side compensation ought to make the module more robust

against any thermal excursions in the experiment

• Modules could be affected by this as both ROIC and sensor become thinner
• We believe LETI to be a viable vendor for this type of work and

collaboration will be on-going to further develop this approach and fine tune the processing on the FE-I4b wafers.

Summary

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BACKUP

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SmallPix layout

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TWEPP 2013 Massimiliano De Gaspari, Medipix

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Massimiliano De Gaspari , Medipix TWEPP 2013

Bump bond development

• Investigate use of backside

compensation with Cea-Leti to remove bowing issue

• Process FE-I4s:

– Front side processing: UBM & micro pillars – Bond front side to carrier wafer – Thin – Backside deposition – Release front side

• UBM on sensors and flipping at

Advacam

• UBM and Micro pillar

– UBM

• TiNiAu
• 0.5 – 1.5µm
• 40µm pitch
• 20µm width (minimum)

– Micro pillars

• Cu post / SnAg Solder
• 50µm pitch
• 25µm diameter
• 8-12µm thickness

FE-I4B with micro-pillars

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Wafer thinning – after bumps

• Front side protection/

planarization:

– UV-curable back grinding tape laminated on bumped wafer.

• Back grinding using diamond

wheels with two different grit sizes (coarse + fine).

• Defect layer left by mechanical

grinding is removed by wet chemical etching or CMP (Chemical Mechanical Polishing).

• Protective tape is UV-exposed

and delaminated.

• Thickness down to 150 µm (200-

mm/8” wafers).

• Total thickness variation (TTV)

with protective tape < 5 µm over wafer.

• Post-grinding defect layer etching

improves mechanical strength of die.

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ALICE modules ALICE1/LHCb readout chip process

• Readout wafer size 200 mm x

725 µm

• Bumping with eutectic solder:

– TiW/Cu/Ni(3 µm)/eut. Sn-Pb(13 µm)

• Bump pitch: x = 50 µm / y =

400 µm

• Wafer thinning to 150 µm
• Dicing to chip size of 13.7 mm

x 15.9 mm

• Picking of known good die
• Number of bumps/chip: 8,192

ALICE sensor chip process

• Detector wafer size 125

mm x 200 µm

• Bump pad metallization:
• TiW/Cu/Ni(3 µm)/eut. Sn-

Pb(3 µm)

• Dicing to chip size of 70.7

mm x 13.9 mm

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Hybridized ALICE assembly

• Five ALICE1/LHCb

readout chips flip chip bonded on ALICE1 detector ladder chip

• Assembly reflow using

formic acid oven

• Chip-to-substrate

distance: 20 µm

• Total number of

bumps/assembly: 40,960

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Advacam & CEA Leti Advacam

• Spin-out company from VTT

– Company goal is to produce hybrid x-ray cameras and offer flip-chip and sensor production service – Hire VTT equipment for process development and production

• Pb/Sn Solder bump

electroplating on 200mm wafers

• Thin film transition metal UBM

– Development to reduce cost

• Flip-chip with FC-150 machines
• Active-edge sensor development

CEA Leti

• One of the largest research
• rganizations in Europe

– 40 start-ups and 265 industrial partners

• 3D Opensource technology
• ffer

– 200 & 300mm capability – TSV’s – Redistribution layer (RDL) – UBM – Interconnections – Component stacking – Packaging with partner collaboration

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Through Silicon Via (TSV). Cu filled. AR3-10 2 to 4 layers routing Damascene thick Copper R o u t i n g o n o r g a n i c Thinning 80 – 100 µm Internal stress monitoring Warp management Temporary bonding on 100 µm thk 200mm wafer including small or large copper pillars µ-bumps and SAC copper pillars Molding & underfilling F2F and B2F Thin die stacking (30um thk). Conformal routing

Organic/silicon rebuilt wafer Routing and via (TPV) Strata stacking and connecting

Silicon on wire

INTEGRATION

3D Packaging Lab / Core competencies at CEA-LETI

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• Visual control
• Back side and front side cleaning
• Preclean + seed layer deposition : Ti 100nm + Cu 400nm
• Photolithography for µbump, negative photoresist
• Flash O2
• Electrochemical deposition (ECD) Cu 10µm + SnAgCu solder

(SAC) 8µm

• Stripping
• Cu 400nm + Ti 100nm wet etch
• SAC reflow

Process Flow

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• Seed layer etch + reflow
• 2 probes resistance measurement =~2.5 Ohm on 2 µbump chain on top metal
• Both wafers looked good with seed etch clear in fields and no metalic residue

between bumps

Wafer inspection post µBump solder reflow and seed etch

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• Flip chipping conducted at ADVACAM to demonstrate front side

processing and bump-bonding

• Boarding mounting and testing at Liverpool*
• Threshold tuning of all the available working modules to date
• Data at 3200e used for estimating the number of dead,

unconnected, noisy and stuck pixels in these modules.

*Marko Milovanovic et al. Pixelfest Manchester

2013

Module ID Dead pixels Cut = 30 ADV-DC-1 2 3 ADV500-DC-2 2 3 ADV2000-DC-2 1 ADV2000-DC-1

untuned

4 9 Defect rate of 0.04% observed so far we will have more module data soon

Module Results for full thickness FEI4b chips

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Bump bond yield

• IBL specification for bump-bonds

– Pitch = 50um – Bump density = 26,880 per ROIC – As built module bad pixels = 0.2% è 54 pixels

• 4 single assemblies mounted on PCBs and characterized
• Data at Tuned Vth = 3200e used to estimate the number of dead,

unconnected, noisy and stuck pixels.

• The number of unconnected bumps was derived from the

Threshold scans with HV ON and OFF.

• ΔNoise (HVOff − HVOn) < cut
• Cut = 20 or 30 electrons
• A pixel was considered dead if it has less than 1e of noise with HV

ON/OFF.

• Noisy pixels were extracted from the HV ON Threshold Sigma plot,

by applying a cut based on the sigma from the mean noise (3σ - 5σ)

• Source scan and Noise Occupancy scan was used to verify this

analysis and potentially identify stuck pixels as well.

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16/05/2014 ¡ UK ¡Pixel ¡MeeEng, ¡October ¡31 ¡2013 ¡ 45 ¡

ADV125-DC-1 Noise distributions with HV OFF and ON

No ¡Fake ¡Fit! ¡

(good ¡separaEon ¡ between ¡distribuEons) ¡

• There is a well defined separation point between noise distributions with HV

ON and OFF - VCal range and step size was properly chosen.

• Pixels having noise difference between HV OFF and ON in the Threshold

scan less than a certain cut (ΔNoise (HVOff − HVOn) < cut) are considered to be unconneted.

• A pixel was considered dead of it has less than 1e of noise with HV ON/

OFF.

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16/05/2014 ¡ UK ¡Pixel ¡MeeEng, ¡October ¡31 ¡2013 ¡ 46 ¡

Source scan and noisy occupancy cross check for ADV125-DC-1

(>1000) ¡ (<1)

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Counting Bad Pixels for all the modules

• For most of the modules, the majority of noisy pixels come from the last two

columns (79, 80) on the right.

• With these two (noisy/damaged) pixel columns removed, the numbers

become:

• ΔNoise (HVOff − HVOn) and applied cuts give the following numbers for all the

modules: If Gaussian expect: 72 2 0.02

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