Innovation to Advance Moores Law Requires Core Technology Revolution - - PowerPoint PPT Presentation

External Use

Innovation to Advance Moore’s Law Requires Core Technology Revolution

UC Berkeley Seminar March 9th, 2012

Klaus Schuegraf, Ph.D.

Chief Technology Officer Silicon Systems Group Applied Materials

External Use

Innovation to Advance Moore’s Law Thank you for coming

2

Semiconductor Value Chain - Equipment Moore’s Law Challenges Core Technology Focus Opportunities for Innovation

External Use 3

INTEGRATED CIRCUITS DEVICES WAFER FAB APPLIED MATERIALS

NAND VERTICAL BIT STACK

DRAM VERTICAL TRANSISTOR

LOGIC FINFET

External Use

Leadership Strategy - Accelerate Innovation

4

Collaborate earlier and deeper with customers on inflections Provide the broadest suite of solutions with unmatched integration benefits Extend the technology roadmap with fast cadence in product innovation Drive to atomic precision on interfaces with multi-chamber platforms Enable faster learning with Maydan Technology Center

Plating Thermal Metals Deposition Etch Inspection Planarization Implant

External Use 5

External Use

Moore’s Law in Context

6

Moore’s Law: Performance, Power Efficiency, Cost

From: W. Nordhaus, Yale

Performance Cost

External Use

Logic Technology Scaling Projection

7

New Fin Material STI Oxide

Identify challenges and opportunities to enable scaling Focus university research on the big problems

Logic Roadmap Scenario 2009 2011 2013 2015 2017 2019 2021 2023 2025 2027

Node and Lg (nm) 32 22 14 10 7 5 3.5 2.5 1.8 1.3 Interconnect CD (nm) 60 40 30 20 15 10 7.5 5 3.5 2.5

III-V FinFET

Gate

STI Oxide

Fin

Planar CMOS FinFET

External Use 8

Inflections Add Complexity and Opportunity

8

Advanced Patterning Advanced Interconnects Wafer-Level Packaging Advanced Transistors

External Use 9

Scaling Increasing Complexity

+

NEXT

5

YEARS LAST

15

YEARS

TODAY

PVD  Metal CVD E-beam inspection Sacrificial films CVD: Hidden films, more steps CMP: New materials, steps, atomic precision Etch: New mtls, high aspect ratio Wafer-level packaging Packaging interposer Optical interconnect Big 3: Logic, DRAM, NAND US-centric innovation Customer consolidation, JV partnerships Logic  Foundry/Fabless NOR  NAND DRAM 8F2  6F2 200mm  300mm Single-wafer processing



Innovation

Epi Single-wafer cleans Copper damascene Low-k dielectric CMP Bumping Deep-UV laser lithography Memory Double patterning Patterning films Lamp-based processing Reflow  HDP DRAM Capacitor Hi-K ALD DPN SiON gate Add to Big 3: Image sensor, MRAM, RRAM Global innovation Extreme customer concentration Fabless  Vertical fabless system houses 300mm  450mm Logic  FinFET NAND  3D NAND DRAM 6F2  3D 4F2 New energy sources: (E-beam, Laser, UV, X-ray) EUV Double patterning for logic Quad patterning for memory Laser-based processing Flowable films New materials: III-V, Ge Universal ALD (metal, dielectric)

External Use

Advanced Transistor Challenges

10

STI Oxide Fin

Spacer Conventional approach: high AR gate Alternative: Spacer transfer Alternative: Selective deposition Challenge: Spacer-k and Hi-k parasitic Fin Formation Precision etch Structural integrity (collapse, erosion, thermal shock) Recess Channel materials Gate Stack Dummy gate considerations Ternary materials Planarization Removal Hi-k scalability Metal gate considerations Workfunction Resisitivity Fill Self-aligned contact Fin Junctions Conformal doping Stressor alternatives Annealing considerations Silicide Barrier modification New materials

External Use

Gate Dielectric Scaling Challenge

11

350 250 180 130 90 65 45 32 22 15 11 7 1 10 TINV (nm) Technology Node (nm) 0.01 0.1 1 10 100 1000 Gate Leakage (Rel.)

Poly/SiON High-k/Metal

Slowed

Thinner EOT requires innovation in interfaces

2 nm

Applied Internal Data

Scaling EOT limited by SiO2 IL

External Use

Interfaces Matter Even More Electrically…

Fully Integrated Gate Stack Air Exposure After Interface Layer

Improved Mobility

Peak Mobility

5 to 10%

Applied Internal Data 12

Less Trap Assisted Tunneling

Fully Integrated Gate Stack Air Exposure After Interface Layer

Gate Leakage Temperature Acceleration

• 30%

Applied Internal Data

ALD High- RadiancePlus RadiancePlus DPN3 Nitridation

Centura cluster enables solution path

External Use

New iL technology improves BTI Reliability

NBTI PBTI

0.01 0.1 0.7 delta Vt @ 1000 sec Vg - Vt (V)

ChemOx IL 3A new IL 5A new IL

0.01 0.1 0.6 @ Vg - Vt (V)

ChemOx IL 3A new IL 5A new IL

Applied Internal Data Applied Internal Data

13

External Use

Advanced Interconnect Challenges(≤20nm)

Reliability Electromigration BLOk-Cu interface Barrier-Cu interface TDDB/BTS Patterning(Overlay, LWR/LER) Interface management Barrier and moisture integrity Capacitance Packaging High modulus at lower k Interface adhesion Integrated k BLOk thickness Integration damage Higher k adhesion layers Architecture Air-gap Single Damascene Non-Damascene Resistance Copper Conformal barriers Liner/barrier Volume Gap-fill Scattering Barrier-Cu interface Grain size Higher aspect ratio Patterning Gap-fill Patterning Pitch division CD distributions, CDU Overlay Pattern integrity Line bending, collapse LWR/LER

External Use

Interconnect Improvement: RC-Delay

15

Conventional Disruptive

Disruptive

Metal-Insulator Barrier Replacement Low-k Diel. Low-k Dielectric Copper

10 20 30 40 50 60 70 80 32nm 22nm 15nm 11nm

RC Delay (ns/mm) Technology Node

RC Delay Outlook Innovate new technologies to resolve RC-delay challenge

External Use

New Process Flow for RC Reduction

SiN BLOk BLOk

16

Low k

Integrated k = Bulk k = No Damage No damage interconnect flow enables pathway to k < 2

Applied Internal Data

0.05 0.10 0.25 0.50 0.75 0.90 0.95 0.99

• 3
• 2
• 1

USG/Cu Interconnect No damage Cu-Low k interconnect Cu-Lowk Conventional flow 15% Damage % Probability

RC Product

Applied Internal Data

External Use

0.05 0.10 0.25 0.50 0.75 0.90 0.95 0.99

• 3
• 2
• 1

1 10 100 1000 10000

17

Selective CVD Metal Caps for EM Enhancement

Applied Internal Data

Selective Metal Cap shows >80x EM improvement

% Probability MTTF (hrs) 80x

300°C, 1.5 MA/cm2

External Use

Innovation to Advance Moore’s Law

18

Semiconductor Value Chain - Equipment Moore’s Law Challenges Core Technology Focus Opportunities for Innovation

External Use

Future of Moore’s Law

19

Problem: Physical limits as features approach 3nm Need: Solutions to advance density, power and performance

• F. Yang, TSMC, VLSI 2004
• S. Bangsaruntip, IBM, IEDM 2009

Extend FinFET Gate all-around 2D  3D Alternative Devices

• G. Dewey, Intel, IEDM 2011

T.-J. King Liu, UCB, IEDM 2009

• S. Salahuddin, UCB, IEDM 2011

External Use

• Packing density:

Unit area per transistor (SRAM equiv.)

• Performance:

Switching delay

• Power:

Switching energy

• Integration Complexity:

Compatibility with Si CMOS

Device Integration Compatibility Vop

*

(V) SS (mV/dec) Delay† (psec) Energy† (fJ) Unit Area (nm2)

CMOS 32 nm

High 0.9 <100 0.2 0.1 28000

CMOS 11 nm

(extrapolated)

High 0.63 <70 0.02 0.03 3500

CMOS 5 nm

(extrapolated)

High 0.55 <70 0.01 0.015 900

New Device

? ? ? ? ? ?

*Vop based on 2011 ITRS Roadmap for LOP

†Inverter FO = 1, logic depth = 10, activity = 0.1 (Philip Wong, Stanford, IEDM 2010)

New Device Scorecard

External Use

Junction Conformal doping Gate Stack Conformal high-k and metal gate Channel New channel materials Patterning Gates and junctions defined at planar level Local contacts and interconnect between planes

“Gnd” “Vdd” “Out” “In”

Future of Moore’s Law: 3D GAA as alternative?

Opportunity for new CMOS architectures with many challenges

External Use

Focus Areas for Research

• Core Technology

– Energy sources – Chemical delivery systems & chemistries – E-beam – Variability management

• Materials

– Screening methods – Alternative materials: Graphene, Metal Oxide, III-V, optical

• Devices

– 100mV switches – High packing density logic – Alternate channel, Optical interconnect, Interposer

• EUV Lithography

22