Technology*Mapping - PDF document

Technology*Mapping Technology*mapping*transforms*one*logic*circuit*model*into* another*one.* What%is%the%difference%between%this%and% synthesis ? Custom*Integrated* Circuits Discrete* Components Programmable* Standard>Cell* Logic Integrated*Circuits 1 Compiler/Programmable*Logic* Comparison 2

F = AB + BC + AC 22V10 PLD 7410 7400 Static 8 x 1 RAM CMOS A Gate A2 F B A1 DO C A0 Lookup Table 3 Logic*Synthesis Logic*Synthesis*(designer*definition):*convert*a*description* of*a*digital*system*in*a*Hardware*Description*Language* (HDL)*to*an*implementation*technology.* Gates Verilog*HDL* description* // Combinational Logic Circuit module cmb_circ(Y, A, B, C); Synthesis input A, B, C; output Y; assign Y = (A&B)|(A&C)|(B&C); endmodule 4

Logic*Synthesis Logic*Synthesis*(designer*definition):*convert*a*description* of*a*digital*system*in*a*Hardware*Description*Language* (HDL)*to*an*implementation*technology.* VHDL*description* Gates* library ieee; use ieee.std_logic_1164.all; entity majority is port ( A, B, C : in std_logic; Y: out std_logic ); Synthesis end majority; ARCHITECTURE a of majority is begin Y <= (A and B) or (A and C) or (B and C); end a; 5 Logic*Circuit*Models 6

Basic*Logic*Gates 7 2:1*Multiplexer 8

Combinational*Building*Blocks 1*bit*Multiplexer*(2:1*MUX) if S = 0, then Y = I0 I0 if S = 1, then Y = I1 Y I1 S Y = I0 S’ + I1 S A[3:0] Muxes*are*often* I0 D[3:0] B[3:0] Y used*to*select* I1 S groups*of*bits* arranged*in*busses. How%many%wires%in%each%bus%? 9 Multiplexers Shannon%Expansion%Theorem • Original*Function: f=x’y’z+x’yz+xy’z+xyz’ • Cofactors: f x’ =z 0 f f x’ = f ( x =0) =y’z+yz = z f x = y ⊕ z 1 f x =f ( x= 1) =y’z+yz’ = y ⊕ z f = x’f x’ + xf x x f=x’z +x ( y ⊕ z ) a b c M 0 0 0 0 a 0 0 0 1 0 M 0 1 0 0 0 1 1 1 b 1 1 0 0 1 1 0 1 0 1 1 0 1 c 1 1 1 1 10

Multiplexers 11 Memory*Device*Architecture • 2 n ×m Device – n inputs*called*“address*lines” – m outputs*called*“data*lines” • Contains*3*Main*Subcircuits: 1) Decoder (Address*Decoder) 1%:%n ×2 n Decoder%Circuit ! 2) Storage*Array (Array*of*1>bit*Storage*Cells) m•2 n :%1Bbit%storage%cell%circuits ! 3) Sense*Amps (Amplifiers*from*Cells*to*Outputs) ! m%:%SingleBEnded%OR Differential%Amplifiers Difference%Between%Memory%Types%(RAM,%ROM,%etc.) is%Primarily%Due%to%Storage%Cell%Implementation 12

Decoder*(Review) n×2 n Device • – n encoded*inputs 2 n decoded*outputs – D 3 A 1 2 × 4 D 2 Decoder D 1 A 0 D 0 A 1 A 0 D 3 D 2 D 1 D 0 0***0 0***0***0***1 0***1 0***0***1***0 1 0 0***1***0***0 1***1 1***0***0***0 13 Decoders*(with*Enable) C0 E A0 C1 C0 A0 1:2 1 0 0 1 Decoder 1 1 1 0 C1 0 X 0 0 E C0 A0 E A1 A0 C3 C2 C1 C0 C1 1 0 0 0 0 0 1 2:4 1 0 1 0 0 1 0 Decoder C2 1 1 0 0 1 0 0 1 1 1 1 0 0 0 A1 0 X X 0 0 0 0 C3 14 E

Decoder A[2:0] Y0 if A= 000 then Y0=1 else Y0=0; Y1 if A= 001 then Y1=1 else Y1=0; Y2 if A= 010 then Y2=1 else Y2=0; Y3 if A= 011 then Y3=1 else Y3=0; Y4 if A= 100 then Y4=1 else Y4=0; Y5 if A= 101 then Y5=1 else Y5=0; if A= 110 then Y6=1 else Y6=0; Y6 if A= 111 then Y7=1 else Y7=0; Y7 15 Amplifiers*(Review) • SingleBEnded%Amplifier – Gain: A v – 1%input%voltage,%1%output%voltage%referenced%to%common%ground A v V in V out =* A v% V in • Differential%Amplifier – Gain: A v – 2%input%voltages,%1%output%voltage%referenced%to%common%ground V 1 + A v V out =* A v% (V 1 >V 2 ) V 2 - Buffer%Generally%%Refers%to%an%Amplifier%with%Unity%Gain%(A v =1) 16

Semiconductor*Memory*Device*Architecture • 2 n ×m Device – n inputs*called*“address*lines” 2 n storage*locations*called*“number*of*words” – – m outputs*called*“data*lines” Storage*Cell*Array A 1 2 × 4 Decoder A 0 Sense*Amps D 4 D 3 D 2 D 1 D 0 17 Memory*example F (A,B,C) = A ⊕ B ⊕ C G = AB + AC + BC 8 x 2 Memory A B C F G A A2 F 0 0 0 0 0 D1 B A1 G 0 0 1 1 0 DO C 0 1 0 1 0 A0 0 1 1 0 1 LookUp Table (LUT) 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 A[2:0] is 3 bit address 1 1 1 1 1 bus, D[1:0] is 2 bit Recall that Exclusive OR ( ⊕ ) is output bus. Location 0 has “00”, A B Y 0 0 0 Location 1 has “10”, 0 1 1 Y = A ⊕ B Location 2 has “10”, 1 0 1 = A xor B 1 1 0 etc…. 18

Logic*Arrays A B C Vcc 19 F G Logic*Arrays A B C What about these? Vcc F G 20

Logic*Arrays A B C What about these? Vcc F G 21 Binary*Adder F (A,B,C) = A B C G = AB + AC + BC These equations look familiar. Recall what a Full Adder is: A B Sum = A B C in Cout = AB + C in A + C in B A B C out C in = AB + C in (A + B) Co Ci S Full Adder (FA) Sum 22

4*Bit*Ripple*Carry*Adder A(3) B(3) A(2) B(2) A(1) B(1) A(0) B(0) A B A B A B A B Cout C(4) C(3) C(2) C(1) C(0) Cin Co Ci Co Ci Co Ci Co Ci S S S S Sum(3) Sum(2) Sum(1) Sum(0) A[3:0] SUM[3:0] + B[3:0] 23 Full*and*Ripple*Adders 24

Fixed>Point*Multipliers 25 Array*Multiplier*Structure 26

Propagation*Delay Y A H A L t phl t plh H Y L 27 Propagation*Delay**(non*inverting) H Y A H A L t plh t phl H Y L 28

Busses 16'bit+Reg 16'bit+Reg 16'bit+Reg 16'bit+Reg 16 16 16 16 BUS 16 Here+we+require+16+wires+and+arbitration+logic Arbitration+logic+ Controls the+flow+of+data 29 Tri>State*Buffer*Types • 3+states+instead+of+2+(0+and+1) • 0,+1,+zE++z+is+“high+impedance”+state • “high+impedance”+is+open+circuit Type+of+3+state+buffers a b a b a b a b c c c c if(c==1’b0) if(c==1’b1) if(c==1’b0) if(c==1’b1) b=~a; b=~a; b=a; b=a; else else else else b=1’bz; b=1’bz; b=1’bz; b=1’bz; IfBstatements%to%explain%behavior%only%(Verilog%HDL) 30

Tri>state*Buffers 31 16'Bit+Bus Example R n R m designated+by+4'Bit+control+word+ nm ,+ie+0110+means+R1++++++R2 16 16 BUS(15:0) 7 6 5 4 3 2 1 0 BUSEN(7:0) 8 8 R0 R1 R2 R3 CLK 1 3 2 1 0 LOAD(3:0) 4 CTL BUSEN 4 8 Arbitration CLK Logic 4 LOAD 32

Making*a*Design*Run*Fast • Speed*is*usually*much*more*important*than*saving* gates. • The*speed*of*a*gate*directly*affects*the*maximum* clock*speed*of*a*digital*system • Gate*speed*is*TECHNOLOGY* dependent – 90nm*CMOS*process*has*faster*gates*than* 130nm*CMOS*process • Implementation*choice*will*affect*Design*speed – A*Custom*integrated*circuit*will*be*faster*than*an* FPGA*implementation. • Design*approaches*will*affect*clock*speed*of*system – Smart*designers*can*make*a*big*difference 33 Summary • Need*to*review*your*Digital*Logic*Design*notes – Basic*Gates,*Boolean*algebra*(algebraic*minimization,*up*to* four*variable*K>maps),*Combinational*building*blocks* (muxes,*decoders,*memories,*adders) • We*will*discuss*Hardware*Description*Languages – Verilog*is*the*language*used*in*the*class • We*will*discuss*modern*implementation*technologies,* primarily*Field*Programmable*Gate*Arrays*(FPGAs) • We*will*discuss*design*strategies*for*making*designs* run*faster,*not*necessarily*take*less*gates. 34