Technology*Mapping - - PDF document

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Technology*Mapping - - PDF document

Oct 29, 2023 356 likes •550 views

Technology*Mapping Technology*mapping*transforms*one*logic*circuit*model*into* another*one.* What%is%the%difference%between%this%and% synthesis ? Custom*Integrated* Circuits Discrete* Components Programmable* Standard>Cell* Logic

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SLIDE 1

Technology*Mapping

Technology*mapping*transforms*one*logic*circuit*model*into* another*one.*What%is%the%difference%between%this%and% synthesis? Discrete* Components Programmable* Logic Custom*Integrated* Circuits Standard>Cell* Integrated*Circuits

1

Compiler/Programmable*Logic* Comparison

2

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SLIDE 2

F = AB + BC + AC

7400 7410 22V10 PLD

A0 A1 A2 8 x 1 RAM A B C DO

F Lookup Table Static CMOS Gate

3

Logic*Synthesis

Logic*Synthesis*(designer*definition):*convert*a*description*

  • f*a*digital*system*in*a*Hardware*Description*Language*

(HDL)*to*an*implementation*technology.*

// Combinational Logic Circuit module cmb_circ(Y, A, B, C); input A, B, C;

  • utput Y;

assign Y = (A&B)|(A&C)|(B&C); endmodule

Verilog*HDL* description* Gates Synthesis

4

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SLIDE 3

Logic*Synthesis

Logic*Synthesis*(designer*definition):*convert*a*description*

  • f*a*digital*system*in*a*Hardware*Description*Language*

(HDL)*to*an*implementation*technology.*

library ieee; use ieee.std_logic_1164.all; entity majority is port ( A, B, C : in std_logic; Y: out std_logic ); end majority; ARCHITECTURE a of majority is begin Y <= (A and B) or (A and C) or (B and C); end a;

VHDL*description* Gates* Synthesis

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Logic*Circuit*Models

6

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SLIDE 4

Basic*Logic*Gates

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2:1*Multiplexer

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SLIDE 5

Combinational*Building*Blocks

1*bit*Multiplexer*(2:1*MUX) if S = 0, then Y = I0 if S = 1, then Y = I1 Y = I0 S’ + I1 S Muxes*are*often* used*to*select* groups*of*bits* arranged*in*busses.

I0 I1 Y S

A[3:0] B[3:0] D[3:0]

I0 I1 Y S

How%many%wires%in%each%bus%?

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Multiplexers

Shannon%Expansion%Theorem

  • Original*Function:

f=x’y’z+x’yz+xy’z+xyz’

  • Cofactors:

fx’ = f(x=0)=y’z+yz = z fx =f(x=1)=y’z+yz’ = y⊕ z f = x’fx’ + xfx f=x’z +x(y⊕ z)

fx’=z fx=y⊕ z f x a b M c a b c M 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1

1

1

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SLIDE 6

Multiplexers

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Memory*Device*Architecture

  • 2n×m Device

–

n inputs*called*“address*lines” – m outputs*called*“data*lines”

  • Contains*3*Main*Subcircuits:

1) Decoder (Address*Decoder)

! 1%:%n ×2n Decoder%Circuit

2) Storage*Array (Array*of*1>bit*Storage*Cells)

! m•2n :%1Bbit%storage%cell%circuits

3) Sense*Amps (Amplifiers*from*Cells*to*Outputs)

! m%:%SingleBEnded%OR Differential%Amplifiers

Difference%Between%Memory%Types%(RAM,%ROM,%etc.) is%Primarily%Due%to%Storage%Cell%Implementation

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SLIDE 7

Decoder*(Review)

  • n×2n Device

–

n encoded*inputs – 2n decoded*outputs

2×4 Decoder

A1 A0 D3 D2 D1 D0 A1 A0 D3 D2 D1 D0

0***0 0***1 1 1***1 0***0***0***1 0***0***1***0 0***1***0***0 1***0***0***0

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Decoders*(with*Enable)

E 2:4 Decoder C0 C1 C2 C3 A0 A1 A0 A0 A1 E C0 C1 C2 C3 1 1 1 1 1 1 X 1 1 X 1 1 1 1 E C0 C1 1:2 Decoder A0 E C0 C1 1 1 1 X 1 1

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SLIDE 8

Decoder

A[2:0] Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 if A= 000 then Y0=1 else Y0=0; if A= 001 then Y1=1 else Y1=0; if A= 010 then Y2=1 else Y2=0; if A= 011 then Y3=1 else Y3=0; if A= 100 then Y4=1 else Y4=0; if A= 101 then Y5=1 else Y5=0; if A= 110 then Y6=1 else Y6=0; if A= 111 then Y7=1 else Y7=0;

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Amplifiers*(Review)

  • Differential%Amplifier

–

Gain: Av – 2%input%voltages,%1%output%voltage%referenced%to%common%ground Vin Vout=*Av%Vin Av

  • SingleBEnded%Amplifier

–

Gain: Av – 1%input%voltage,%1%output%voltage%referenced%to%common%ground V1 Vout=*Av%(V1>V2) Av V2

+

  • Buffer%Generally%%Refers%to%an%Amplifier%with%Unity%Gain%(Av=1)

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SLIDE 9

Semiconductor*Memory*Device*Architecture

  • 2n×m Device

– n inputs*called*“address*lines”

– 2n storage*locations*called*“number*of*words”

– m outputs*called*“data*lines”

2×4 Decoder

A1 A0 D1 D2 D3 D4 D0 Storage*Cell*Array Sense*Amps

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Memory*example

F (A,B,C) = A ⊕ B ⊕ C G = AB + AC + BC

A B C F G 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Recall that Exclusive OR (⊕) is

A B Y 0 0 0 0 1 1 1 0 1 1 1 0

Y = A⊕B = A xor B

A0 A1 A2 8 x 2 Memory A B C DO

G LookUp Table (LUT)

D1

F A[2:0] is 3 bit address bus, D[1:0] is 2 bit

  • utput bus.

Location 0 has “00”, Location 1 has “10”, Location 2 has “10”, etc….

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SLIDE 10

Logic*Arrays

Vcc

A B C F G

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Logic*Arrays

Vcc

A B C F G

What about these?

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SLIDE 11

Logic*Arrays

Vcc

A B C F G

What about these?

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Binary*Adder

F (A,B,C) = A B C G = AB + AC + BC These equations look familiar. Recall what a Full Adder is:

A B S Ci Co

Cin A B Cout Sum

Sum = A B Cin Cout = AB + Cin A + Cin B = AB + Cin (A + B) Full Adder (FA)

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SLIDE 12

4*Bit*Ripple*Carry*Adder

A B S Ci Co A B S Ci Co A B S Ci Co A B S Ci Co

Cin A(0) Cout B(0) A(1) B(1) A(2) B(2) A(3) B(3) C(0) C(1) C(2) C(3) C(4) Sum(0) Sum(1) Sum(2) Sum(3)

A[3:0] B[3:0] SUM[3:0]

+

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Full*and*Ripple*Adders

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SLIDE 13

Fixed>Point*Multipliers

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Array*Multiplier*Structure

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SLIDE 14

Propagation*Delay

A A Y H L Y H L tphl tplh

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A A Y H L Y H L tplh tphl

Propagation*Delay**(non*inverting)

H

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SLIDE 15

Busses

16'bit+Reg

16 16 16 16 16

BUS

Here+we+require+16+wires+and+arbitration+logic Arbitration+logic+Controls the+flow+of+data

16'bit+Reg 16'bit+Reg 16'bit+Reg

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Tri>State*Buffer*Types

  • 3+states+instead+of+2+(0+and+1)
  • 0,+1,+zE++z+is+“high+impedance”+state
  • “high+impedance”+is+open+circuit

Type+of+3+state+buffers

a b c a b c a b c a b c

if(c==1’b1) b=a; else b=1’bz; if(c==1’b1) b=~a; else b=1’bz; if(c==1’b0) b=a; else b=1’bz; if(c==1’b0) b=~a; else b=1’bz;

IfBstatements%to%explain%behavior%only%(Verilog%HDL)

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SLIDE 16

Tri>state*Buffers

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16'Bit+Bus

Example Rn Rm designated+by+4'Bit+control+word+nm,+ie+0110+means+R1++++++R2

BUS(15:0) BUSEN(7:0) CLK LOAD(3:0)

16 16 8 8

7 6 5 4 3 2 1

R0 R1 R2 R3

1 4

3 2 1

CTL CLK BUSEN LOAD

4 8 4

Arbitration Logic

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SLIDE 17

Making*a*Design*Run*Fast

  • Speed*is*usually*much*more*important*than*saving*

gates.

  • The*speed*of*a*gate*directly*affects*the*maximum*

clock*speed*of*a*digital*system

  • Gate*speed*is*TECHNOLOGY* dependent

– 90nm*CMOS*process*has*faster*gates*than* 130nm*CMOS*process

  • Implementation*choice*will*affect*Design*speed

– A*Custom*integrated*circuit*will*be*faster*than*an* FPGA*implementation.

  • Design*approaches*will*affect*clock*speed*of*system

– Smart*designers*can*make*a*big*difference

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Summary

  • Need*to*review*your*Digital*Logic*Design*notes

– Basic*Gates,*Boolean*algebra*(algebraic*minimization,*up*to* four*variable*K>maps),*Combinational*building*blocks* (muxes,*decoders,*memories,*adders)

  • We*will*discuss*Hardware*Description*Languages

– Verilog*is*the*language*used*in*the*class

  • We*will*discuss*modern*implementation*technologies,*

primarily*Field*Programmable*Gate*Arrays*(FPGAs)

  • We*will*discuss*design*strategies*for*making*designs*

run*faster,*not*necessarily*take*less*gates.

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