Stress-Aware Routing to Mitigate Aging Effects in SRAM-based FPGAs - - PowerPoint PPT Presentation

Stress-Aware Routing to Mitigate Aging Effects in SRAM-based FPGAs

𝟑𝟕𝐮𝐢 International Conference on Field- Programmable Logic and Applications Lausanne, Switzerland, Aug. 29th –Sep. 2nd, 2016 Behnam Khaleghi𝟐, Behzad Omidi𝟐, Hussam Amrouch𝟑, Joerg Henkel𝟑 and Hossein Asadi𝟐

1

Sharif University of Technology, Iran

2

Karlsruhe Institute of Technology, Germany

Nano-CMOS Challenges

2/23

Nano-CMOS Era Area & Cost  Reliability  Implementation Mistakes Wear-out, etc. Radiations, Noise Lightning, etc. Aging External Disturbances Component Defects Power Density  Temperature

Drain(p) Source(p) +

• Basic Concepts: Aging Phenomenon
• Aging
• Bias Temperature Instability (BTI)
• Negative BTI

pMOS type

• Positive BTI nMOS type
• Hot Carrier Induced Degradation (HCID)
• Negative HCID

pMOS type

• Positive HCID nMOS type
• Other types:
• Time Dependent Dielectric Breakdown
• Electro migration

3/23

Si Si Si H H H

+ + + +

• |𝑊

𝑕𝑡| = 0

|𝑊

𝑕𝑡| = 𝑊𝑒𝑒

Drain(n) Source(n)

𝑊

𝑕

𝑊

𝑒

• 𝐽𝑐𝑣𝑚𝑙

𝐽𝑕𝑏𝑢𝑓 𝐽𝑑ℎ𝑏𝑜𝑜𝑓𝑚

Basic Concepts: BTI

• Bias Temperature Instability
• Includes two phases:

 Stress time

• Applied voltage to Gate of MOS
• 𝑊

𝑕𝑡 = 𝑊 𝑒𝑒 Threshold voltage ↑

 Recovery time

• Remove voltage to Gate of MOS
• 𝑊

𝑕𝑡 = 0  Threshold voltage ↓

• Ideal Duty Cycle (DC) = 0.5
• Attention:

∆𝑾𝒖𝒊 𝑺𝒇𝒅𝒑𝒘𝒇𝒔𝒛−𝑼𝒋𝒏𝒇 < ∆𝑾𝒖𝒊 𝑻𝒖𝒔𝒇𝒕𝒕−𝑼𝒋𝒏𝒇

Stress Recovery

Time Threshold Voltage

Remove Voltage 4/23

𝑇. 𝐿𝑗𝑏𝑛𝑓ℎ𝑠, 𝐵. 𝐵𝑛𝑝𝑣𝑠𝑗, 𝑏𝑜𝑒 𝑁. 𝐶. 𝑈𝑏ℎ𝑝𝑝𝑠𝑗, Investigation of nbti and pbti induced aging in different lut implementations, 𝐽𝑜 𝐽𝑜𝑢𝑚. 𝐷𝑝𝑜𝑔𝑓𝑠𝑓𝑜𝑑𝑓 𝑝𝑜 𝐺𝑗𝑓𝑚𝑒 − 𝑄𝑠𝑝𝑕𝑠𝑏𝑛𝑛𝑏𝑐𝑚𝑓 𝑈𝑓𝑑ℎ𝑜𝑝𝑚𝑝𝑕𝑧 (𝐺𝑄𝑈), 2011.

Basic Concepts: BTI Impacts

• Negative Effects of BTI

Timing Violation

5/23

ID Reduction

(Id∝ Vdd − Vth)

Delay Increase

Transient & Permanent Fault

Critical Charge Reduction Soft Error Sensitivity VthShift

Motivation: FPGA Susceptibility

• FPGA High Susceptibility to Aging
• Circuit varies with each new reconfig.
• Both logic and configuration memory
• Configuration memory  permanent fault
• Too many resources to monitor

6/23

Output

SRAM

c

Flip- Flop Mux

LUT I1 I2 I3 In

Logic: 20%-30% Routing: 80%-70%

W1 Wn E1 En S1 Sn N1 Nn . . . . . . . . .

. . .

LB LB SM SM LB LB LB LB SM SM LB LB LB CB CB CB CB CB CB CB CB CB CB CB CB

Aging in Routing more Challenging.

Motivation: Routing Vulnerability

Flash Translation Layer Algorithm in SSD Controllers (Min size Virtex-II)

5 10 15 20

x 10000

Routing 1 Routing 0 LUT 1 LUT 0

• 𝑄𝑡𝑢𝑠𝑓𝑡𝑡(𝑆𝑝𝑣𝑢𝑗𝑜𝑕) ≈ 𝑄0→0 + 𝑄

1→1 = 0.92 × 0.92 + 0.08 × 0.08 = 0.85

• 𝑄

𝑡𝑢𝑠𝑓𝑡𝑡(𝑀𝑉𝑈) ≈ 𝑄 0→0 + 𝑄 1→1 = 0.41 × 0.41 + 0.59 × 0.59 = 0.52 7/23

Motivation: Routing Vulnerability

• Routing SRAMs are within Circuit Critical Path
• Not for LUTs

8/23

0% 2% 4% 6% 8% 10% 12% 14% 16% 18%

1 2 3 4 5 6 7 8 9 10

Aging Induced Delay

Year

PG-Mux PG-Buffer PG-Combined TMG-Mux TMG-Buffer TMG-Combined LUT

LUT SB MUX

Proposed Method: Duty Cycle

• Optimal Duty Cycle
• SRAMDC = 0.5
• So, associated SB transistor

9/23

• Configuration Cells in Consecutive Reconfigurations

Proposed Method: Reconfigurations

Prev.0 Prev.1 New.1 New.0

 Invertible  0 → 1  1 → 0 Noninvertible Zero Overlapping 0 Overlapping 1

10/23

Proposed Method: Base Architecture

• FPGA Architecture and Structures in Proposed Method

Bi (top) & Uni- Directional SM (bottom) 11/23

Island-Style Architecture

Bi (top) & Uni- Directional SB (bottom)

• Switch-Box: Buffer Based
• Direct path enabling

Proposed Method: Cell Inversion

12/23 1 1 1 1 1 1

• Switch-Box: Multiplexer Based
• Hamming distance concept

Proposed Method: Cell Inverting

13/23

1 1 1 1

6 Transistors Inverted 2 SRAMs Inverted 0 Hotspot Transistor 4 Transistors Inverted 1 SRAM Inverted 1 Hotspot Transistor 4 Transistors Inverted 1 SRAM Inverted 2 Hotspot Transistors

Proposed Method

14/23

Proposed Method

• Assigning Initial Cost for (prev.) Active SRAMs
• OverlapingSRAM > Threshold → Use Scheme 1
• OverlapingSRAM < Threshold → Use Scheme 2

Scheme 1

• Routing by Assigning Higher Cost

to Previous Used Cells

• Inverting All Unused Cells

Scheme 2

• Routing by Avoiding Using

Previous Active (0 or 1) Cells

• Inverting All Unused Cells

Proposed Method: Overall Flow

Start

Read Previous Configuration (Configprev) Read Overlapping Configuration (Configoverlap)

Cost ← Assign_Priority (Muxi ∈ Configprev)

Configoverlap < threshold Routing Succeeded?

Invert Unused Cells of New Design(0 → 1)∗

Improper Connection?

Yes No

Undo Inverted bits

Yes

* Unconditional 1 0 inverting

All Unused Cells Checked?

No Yes 15/23

Update New Design’s Configuration

Muxi ← invert(Muxi ∈ Configoverlap)

End

Reduce the Cost

• f Configprev

No No Yes

Proposed Method: Threshold Value

10 20 30 40 50 60 70 80 90 100 1 2 3 4 5 6 7 8 9 10 11 alu4 apex2 apex4 bigkey clma des diffeq dsip elliptic ex5p ex1010 frisc misex3 pdc s298 s38417.1 s38581 seq spla tseng

100 100 23.8 7.7 2.9 1.2 0.5 0.2 0.1 0.05 0.02 0.01

10 20 30 40 50 60 70 80 90 100 1 2 3 4 5 6 7 8 9 10 11

Placing Benchmarks with Different Seed Numbers Average Overlapping Configuration Bit

Shared Cells

(used configuration bits)

# of Reconfigurations with Different Placements # of Reconfigurations with Different Placements Shared Cells

(used configurations bit)

16/23

Experimental Setup

Tools

Aging Impact Measurement Clustering, Placement and Routing HSpice VPR 7.0 17/23

Devices

Logic Array Routing Channel Width Minimum 1.2x Min.

Architecture

Island Style SB Type Uni and Bi Directional Switch Matrix Topology Subset SB Structure Buffer/ Multiplexer Wire Segment Length L=1

Experimental Setup (cont.)

• Assumption
• Circuits reconfigured in identical time intervals
• Same Circuit is Reconfigured
• Using different placement seeds
• FPGA array size and channel width is maintained
• Same circuit with different placement and routing
• Analogous to using different circuits
• VPR tool modified to generate bitstream after routing each circuit

18/23

Results

• Stress Time Reduction (Duty Cycle)
• Hot Spot Elimination (Required Reconfigurations)

0.0 0.5 1.0

Duty y Cyc ycle

Mux-Conv Mux-Proposed Buffer-Conv Buffer-Proposed 5 10 15

Reconf nfig iguratio ion

Mux-Conv Mux-Proposed Buffer-Conv Buffer-Proposed

Mux-based Buffer-based

40% 41%

Mux-based Buffer-based

63% 57%

19/23

Results (cont.)

• Aging Induced Delay (Average)
• Aging Induced Delay (Worst)

0% 5% 10% Aging Induced Delay Base 3year Proposed 3year Base 10year Proposed 10year 0% 5% 10% 15% 20%

Improvement 3 years 10 years

3 years 10 years 8.7% 17.52% 3 years 10 years 9.72% 18.32% 20/23 3 years (OPT)

10 years (OPT)

11.15% 19.66%

Results (cont.)

• Performance Overhead
• Lifetime Improvement

50 100 150 200 250 300

Frequency (MHz)

Mux-Conv Mux-Proposed Buffer-Conv Buffer-Proposed 5 10 15 20 25 4 5 6 7 8 9 10 Proposed Meth thod (year) Baselin ine lifeti time (year)

Mux based

Buffer based

0.2%

0%

21/23

Future Work

• Generalization
• Commercial FPGA Parameters
• SB multiplexer
• Size, pass gate vs. transmission, two-level versus tree-based
• Wire length
• Switch matrix topology
• Impact of Temperature Distribution, Process Variation, etc.
• Impact on Soft Error Rate

22/23

Questions

Thanks for Your Patience!