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Slides for Lecture 21
ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng
Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slides for Lecture 21 ENEL 353: Digital Circuits Fall 2013 Term - - PowerPoint PPT Presentation
Slides for Lecture 21 ENEL 353: Digital Circuits Fall 2013 Term - - PowerPoint PPT Presentation
Slides for Lecture 21 ENEL 353: Digital Circuits Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 28 October, 2013 slide 2/14 ENEL 353 F13 Section 02 Slides
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ENEL 353 F13 Section 02 Slides for Lecture 21
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Today’s Lecture
Critical paths and short paths, finding overall tpd and tcd. Examples of overall tpd and tcd calculations. Glitches. Related reading in Harris & Harris: Sections 2.9.1, 2.9.2.
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ENEL 353 F13 Section 02 Slides for Lecture 21
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Overall tpd and tcd calculations
Suppose a combinational system is built by wiring together some combinational elements. C L C L C L C L If we have tpd and tcd data for each of the elements, how can we find overall values of tpd and tcd for the system as a whole? We’ll see that solving this problem involves concepts called the critical path and the short path.
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ENEL 353 F13 Section 02 Slides for Lecture 21
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A simple example of tpd and tcd calculations
Y A B C D gate tpd tcd AND 50 35 OR 60 45 (Times given in ps.) What is the critical path for this circuit? What is the short path? What is the overall tpd? What is the overall tcd?
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ENEL 353 F13 Section 02 Slides for Lecture 21
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Another simple example of tpd and tcd calculations
A B C D E Y Timing data in ps . . . gate tpd tcd NOT 15 10 4-input AND 50 25 2-input OR 30 22 What is the critical path for this circuit? What is the short path? What are the overall tpd and tcd? What important point is being made in this example?
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ENEL 353 F13 Section 02 Slides for Lecture 21
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A third simple example of tpd and tcd calculations
A B C D E Y n1 n2 Timing data in ps . . . gate tpd tcd NOT 15 10 2-input AND 31 25 3-input AND 40 30 2-input OR 42 32 What are the overall tpd and tcd?
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ENEL 353 F13 Section 02 Slides for Lecture 21
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Timing data for textbook 4:1 mux examples
Gate tpd (ps) NOT 30 2-input AND 60 3-input AND 80 4-input OR 90 tristate (A to Y ) 50 tristate (EN to Y ) 35 Sometimes a gate can respond faster to one of its inputs than to another. The tristate buffer is an example
- f that.
A Y EN All of the data is made up for the purpose of setting up the mux design examples. (That’s also true about other examples in this lecture.) Real timing depends on dimensions and chemical composition of transistors, layout of gates, and other factors.
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For these 4:1 mux designs, find tpd from the S inputs to the
- utput, and also from the D inputs to the output.
S1 D0 D1 D2 D3 Out S0 D2 D3 Out S1 S0 D0 D1
Image is taken from Figure 2.73 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.
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ENEL 353 F13 Section 02 Slides for Lecture 21
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One more 4:1 mux example
S0 D0 D1 D2 D3 S1 Y
2:1 mux 2:1 mux 2:1 mux
For these 4:1 mux designs, find tpd from the S inputs to Y , and also from the D inputs to Y .
Image is taken from Figure 2.74 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc. Note: The textbook gives answers in nanoseconds, but clearly they should be in picoseconds.
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ENEL 353 F13 Section 02 Slides for Lecture 21
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Glitches
Y n1 n2 A n3 B C What is Y when (A,B,C) = (1,1,1)? What about (A,B,C) = (1,1,0)? Suppose the delays are 30 ps for NOT, 50 ps for AND, and 60 ps for OR. Let’s make a timing diagram to show what happens to Y when (A,B,C) goes from (1,1,1) to (1,1,0).
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ENEL 353 F13 Section 02 Slides for Lecture 21
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Are glitches bad?
In certain specialized digital design problems, avoidance of glitches in combinational outputs is very important. Usually, though, glitches are not a concern, and what really matters in timing of combinational logic is making sure that
- verall propagation delay is not long.
(Sometimes low power consumption is even more important than small propagation delay.) In Section 2.9.2, Harris & Harris present a method based on K-maps that can sometimes be used to make circuits glitch-free. We’re not going to study that in ENEL 353.
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ENEL 353 F13 Section 02 Slides for Lecture 21
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Combinational versus Sequential Logic
This is review: The outputs of a combinational logic circuit depend
- nly the current values of its inputs.
The outputs of a sequential logic circuit depend on the history of its input values. We’ve just seen that the above definition of combinational logic is very slightly untrue, due to very tiny delays. However, sequential logic is totally different. Outputs may depend on the history of input values indefinitely far back in the past—minutes, hours, or days, not just picoseconds.
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