Slides for Lecture 21 ENEL 353: Digital Circuits Fall 2013 Term - PowerPoint PPT Presentation

Slides for Lecture 21 ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 28 October, 2013

slide 2/14 ENEL 353 F13 Section 02 Slides for Lecture 21 Previous Lecture Completion of decoder-with-enable examples. Introduction to timing of combinational logic; propagation and contamination delays.

slide 3/14 ENEL 353 F13 Section 02 Slides for Lecture 21 Today’s Lecture Critical paths and short paths, finding overall t pd and t cd . Examples of overall t pd and t cd calculations. Glitches. Related reading in Harris & Harris: Sections 2.9.1, 2.9.2.

slide 4/14 ENEL 353 F13 Section 02 Slides for Lecture 21 Overall t pd and t cd calculations Suppose a combinational system is built by wiring together some combinational elements. C C L L C L C L If we have t pd and t cd data for each of the elements, how can we find overall values of t pd and t cd for the system as a whole ? We’ll see that solving this problem involves concepts called the critical path and the short path .

slide 5/14 ENEL 353 F13 Section 02 Slides for Lecture 21 A simple example of t pd and t cd calculations gate t pd t cd A AND 50 35 B OR 60 45 C Y (Times given D in ps.) What is the critical path for this circuit? What is the short path? What is the overall t pd ? What is the overall t cd ?

slide 6/14 ENEL 353 F13 Section 02 Slides for Lecture 21 Another simple example of t pd and t cd calculations A Timing data in ps . . . B gate t pd t cd C NOT 15 10 D 4-input AND 50 25 Y 2-input OR 30 22 E What is the critical path for this circuit? What is the short path? What are the overall t pd and t cd ? What important point is being made in this example?

slide 7/14 ENEL 353 F13 Section 02 Slides for Lecture 21 A third simple example of t pd and t cd calculations Timing data in ps . . . A n1 gate t pd t cd B NOT 15 10 Y C 2-input AND 31 25 D 3-input AND 40 30 n2 E 2-input OR 42 32 What are the overall t pd and t cd ?

slide 8/14 ENEL 353 F13 Section 02 Slides for Lecture 21 Timing data for textbook 4:1 mux examples Sometimes a gate can Gate t pd (ps) respond faster to one of its NOT 30 inputs than to another. The 2-input AND 60 tristate buffer is an example 3-input AND 80 of that. 4-input OR 90 EN tristate ( A to Y ) 50 tristate (EN to Y ) 35 A Y All of the data is made up for the purpose of setting up the mux design examples. (That’s also true about other examples in this lecture.) Real timing depends on dimensions and chemical composition of transistors, layout of gates, and other factors.

For these 4:1 mux designs, find t pd from the S inputs to the output, and also from the D inputs to the output . S 1 S 0 S 1 S 0 D 0 D 0 D 1 D 1 D 2 Out D 3 D 2 D 3 Out Image is taken from Figure 2.73 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed. , c � 2013, Elsevier, Inc.

slide 10/14 ENEL 353 F13 Section 02 Slides for Lecture 21 One more 4:1 mux example S 0 For these 4:1 mux designs, find t pd from the S inputs D 0 to Y , and also from the D S 1 inputs to Y . D 1 Image is taken from Figure 2.74 from Harris D. M. and Harris S. 2:1 mux Y L., Digital Design and Computer Architecture, 2nd ed. , c � 2013, D 2 Elsevier, Inc. 2:1 mux Note: The textbook gives answers in nanoseconds, but clearly they should be in D 3 picoseconds. 2:1 mux

slide 11/14 ENEL 353 F13 Section 02 Slides for Lecture 21 Glitches A n2 C Y n1 B n3 What is Y when ( A , B , C ) = (1 , 1 , 1) ? What about ( A , B , C ) = (1 , 1 , 0) ? Suppose the delays are 30 ps for NOT, 50 ps for AND, and 60 ps for OR. Let’s make a timing diagram to show what happens to Y when ( A , B , C ) goes from (1 , 1 , 1) to (1 , 1 , 0) .

slide 12/14 ENEL 353 F13 Section 02 Slides for Lecture 21 Are glitches bad? In certain specialized digital design problems, avoidance of glitches in combinational outputs is very important. Usually, though, glitches are not a concern, and what really matters in timing of combinational logic is making sure that overall propagation delay is not long. (Sometimes low power consumption is even more important than small propagation delay.) In Section 2.9.2, Harris & Harris present a method based on K-maps that can sometimes be used to make circuits glitch-free. We’re not going to study that in ENEL 353.

slide 13/14 ENEL 353 F13 Section 02 Slides for Lecture 21 Combinational versus Sequential Logic This is review: The outputs of a combinational logic circuit depend only the current values of its inputs. The outputs of a sequential logic circuit depend on the history of its input values. We’ve just seen that the above definition of combinational logic is very slightly untrue, due to very tiny delays. However, sequential logic is totally different . Outputs may depend on the history of input values indefinitely far back in the past —minutes, hours, or days, not just picoseconds.

slide 14/14 ENEL 353 F13 Section 02 Slides for Lecture 21 Upcoming topics Introduction to sequential logic. SR and D latches. Related reading in Harris & Harris: Sections 3.1, 3.2.1, 3.2.2.