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Shared-clock methodology for time-triggered multi-cores Keith F. Athaide Project supervisor: Michael J. Pont Technical supervisor: Devaraj Ayavoo Communicating Process Architectures (CPA) 2008 8 th -10 th September 2008 Overview Aims

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Shared-clock methodology for time-triggered multi-cores Keith F. Athaide

Project supervisor: Michael J. Pont Technical supervisor: Devaraj Ayavoo

Communicating Process Architectures (CPA) 2008 8th-10th September 2008

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Overview

 Aims  Execution policies

– Co-operative – Pre-emptive

 Execution architectures  Shared-clock architecture

– Algorithm for non-broadcast topologies

 Multi-processor microcontroller architecture  Case study description  Results  Conclusions

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Aims

 Maintain the predictability and robustness of co-operative

single-processor systems

– Custom system-on-chip (SoC) – Time-triggered applications

 Heterogeneous processors  How to synchronise the different processors?

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Execution policy

 System has many functions  Functions often decomposed into discretely executing

blocks called tasks

– Periodic or aperiodic tasks

 Periodic tasks may have static or dynamic periods  Tasks have deadlines  Tasks are executed according to a policy

– Co-operative execution policy – Pre-emptive execution policy

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Co-operative execution policy

Time Time  Tasks must yield control when required  Resource sharing needs no complex locking

mechanisms

– Same processor, one execution thread

 System responsiveness inversely related to longest task

execution time

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Pre-emptive execution policy

Time  Tasks can interrupt each other  Interruption controlled by priorities  Predictability dependent on uniformity in pre-empting

instructions

 Problems such as priority inversion

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Scheduler architectures

 Event-triggered

– Multiple events – Feasibility depends on

 the number of events expected  the number of events serviceable by hardware

– “Construct by correction”

 Time-triggered

– Single event – Other events sensed by polling – “Correct by construction” – Can be power hungry

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Shared-clock architecture

Receive Tick Send ACK Run tasks Slaves Timer Overflow Send Ticks Run tasks Receive ACKs Master Timer Overflow Hardware [overflow]

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Shared-clock non-broadcast topology

 Existing implementations

need communication topologies supporting broadcasts

– Buses like CAN

 Can be simulated by

point-to-point transmissions

– Hardware or software

 Tree broadcast

– MPI collective

communication algorithm

 Lag due to point-to-point

transmissions

a d b c e g h f i g a d h e b c f i

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Multiprocessor architecture

 Network Interface Module (NIM)

– Messaging component as peripheral or co-processor

 Debug cluster

– Write to memories – Set breakpoints, stepping, etc.

Processor Debug Messaging peripheral Timer GPIO

NIM

Memory

Cluster Cluster Network-on-chip (NoC) NIM Cluster NIM Cluster NIM

Processor

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Network interface modules (NIMs)

 Asynchronous communication  Error detection

– 12-bit checksums (CRCs)

 No automatic error correction

– Errors cause no extra communication – Software notes and corrects errors

 Static routing  Serial-parallel communication  Variable number of channels  Lack of predictability in

communication latency might affect

verall predictability of the shared-

clock system

Transport Network Data link Channel Channel

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PH Processor

 Single interrupt

– Built for time-triggered applications – Multiplexed from any number of sources

 Soft-core processor (VHDL source available)  32-bit reduced instruction set computer (RISC)  MIPS I ISA (excluding patented instructions)  Harvard architecture  32 registers  5-stage pipeline

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Hardware implementation

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Hardware usage of NIMs

1 2 3 4 600 650 700 750 800 Bits per channel 6 8 16 Number of channels Hardware slices used

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Case study description

 Nine nodes

– Mesh topology

 Three scheduler types

– SCH1: P1 as master; P1

sends Ticks only when previous is acknowledged

– SCH2: P1 as master; P1

sends Ticks in turn

– SCH3: Tree broadcast

 Relative times measured P5 P2 Debug P6 P7 P3 P4 P0 P1 P1 P0 P4 P3 P7 P2 P6 P5

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Timer sense times (microseconds)

P0 P2 P3 P4 P5 P6 P7 50 100 150 200 250 300 SCH1 SCH2 SCH3

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Timer sense times for SCH3 (microseconds)

P0 P3 P4 P2 P7 P5 P6 10 20 30 40 50 60 70 80

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Timer sense time jitter (microseconds)

P0 P2 P3 P4 P5 P6 P7 0.5 1 1.5 SCH1 SCH2 SCH3 SCH3 (local)

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Timer sense time jitter in SCH3 (microseconds)

P0 P3 P4 P2 P7 P5 P6 0.5 1 1.5 P1 local

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