Semiconductor Wafer Fabrication and Port Services James R. Morrison - - PowerPoint PPT Presentation

▶
semiconductor wafer fabrication
SMART_READER_LITE
LIVE PREVIEW

Semiconductor Wafer Fabrication and Port Services James R. Morrison - - PowerPoint PPT Presentation

Jan 08, 2023 170 likes •400 views

Design of Complex Stochastic Systems: Semiconductor Wafer Fabrication and Port Services James R. Morrison KAIST, Department of Industrial and Systems Engineering xS3D Lab Students: Seunghwan Jung, Jonghoe Kim, Minsung Kim and Kyungsu Park 2 nd

slide-1
SLIDE 1

James R. Morrison KAIST, Department of Industrial and Systems Engineering xS3D Lab Students: Seunghwan Jung, Jonghoe Kim, Minsung Kim and Kyungsu Park

Design of Complex Stochastic Systems: Semiconductor Wafer Fabrication and Port Services

2nd KI International Symposium, September 4 - 9, 2008

slide-2
SLIDE 2

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 2

Presentation Overview

  • Part I: Design of stochastic systems
  • System description: Photolithography clusters in computer chip

fabrication

  • Why does a system-level and stochastic perspective matter?
  • Design for throughput
  • Part II: Design of service systems
  • Port system decoupling leads to service concept
  • Concluding remarks
slide-3
SLIDE 3

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 3

System Description: Photolithography (1)

  • Semiconductor wafer/LCD fabrication are key industries
  • 2007 worldwide revenue: W270x109 (US$270 billion)
  • 2007 Samsung Electronics revenue: W21x109 (US$21 billion)
  • 2007 Korean GDP: ~ W1,000x109 (US$ 1 trillion)
  • State-of-the-art fabricator construction: ~ US$3 billion
  • Photolithography cluster tools
  • Key toolset in semiconductor wafer fabrication
  • Typically a fabricator bottleneck (even with dozens of tools)
  • Cost: ~ W20x109 (US$20 million)

[1] Gartner Research, http://www.gartner.com, [2] CIA World Fact Book [3] EE Times Asia, http://www.eetasia.com, 2007/07/20, [4] Scanner image courtesy of ASML

slide-4
SLIDE 4

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 4

System Description: Photolithography (2)

  • Operation of a of photolithography cluster tool
  • Process modules coat each wafer with photosensitive films
  • Photolithography scanner exposes the film to a light pattern
  • Process modules develop the image on the film

Wafer path for coating Wafer path for develop Scan

slide-5
SLIDE 5

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 5

System Description: Photolithography (3)

  • Several modules may be devoted to a single process
  • Scanner will be the system bottleneck (least throughput potential)
  • Process time for wafer j in module mi is a constant tj

i

  • Wafers of different kinds may require different process times
  • May have a buffer before the bottleneck (scanner)

m1 m5 mA

2

mB

2

mA

3

m4 mB

8

mA

8

mC

7

mB

7

mA

7

mB

6

mA

6

mB

3

mC

3

slide-6
SLIDE 6

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 6

System Description: Photolithography (4)

  • Design question: When should the robots advance the

wafers?

  • Design of steady-state operation
  • Axiomatic design has shown that periodic operation is a good design1
  • Cyclic (periodic) robot schedule is throughput optimal2
  • Design of transient operation?
  • Transients are generally ignored, and if not…
  • Typical objective is to reestablish steady state operation

[1] Hilario L. Oh and Tae-Sik Lee, “A synchronous algorithm to reduce complexity in wafer flow,” Proceedings of the 1st International Conference on Axiomatic Design (ICAD), pp. 87-92, June 21-23, 2000. [2] M. Dawande, N. Geismar and S. Sethi, “Dominance of cyclic solutions and some open problems in scheduling bufferless robotic cells,” SIAM Review, vol. 47, pp. 207-721, 2005.

slide-7
SLIDE 7

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 7

System-Level Perspective (1)

  • Good steady-state design ensures maximum throughput

potential (this is what the tool supplier quotes as speed)

  • In practice:
  • Modules may require a setup between different types of wafers
  • Modules conduct self-cleaning operations
  • Photolithography scanner pauses production when settings change
  • Tool must be emptied before maintenance and filled after
  • Production may wait while monitor (test) wafers are run
  • These events may be considered to occur randomly
slide-8
SLIDE 8

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 8

System-Level Perspective (2)

Throughput Potential and Non Steady-State Phenomenon

80 wph

Wafers Per Hour

Ideal steady state Return from maintenance

69 wph

Module clean and monitor Wafer to wafer interactions

61 wph 55 wph 0 wph

Non steady-state events cause dramatic loss!

[1] James R. Morrison, Beverly Bortnick and Donald P. Martin, “Performance evaluation of serial photolithography clusters: Queueing models, throughput and workload sequencing,” Proceedings of the 2006 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Boston, MA, pp. 44-49, May 2006. *2+ James R. Morrison and Donald P. Martin, “Performance evaluation of photolithography cluster tools: Queueing and throughput models,” OR Spectrum (Springer), Vol. 29, No. 3, pp. 375-389, July 2007.

Actual throughput

Actual throughput x 1.45 = Ideal throughput

slide-9
SLIDE 9

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 9

Axiomatic Design at the System Level (1)

  • Goal:
  • Design photolithography cluster tool
  • Take a system-level approach (explicitly address non steady-state)
  • Constraints:
  • Module process times are known and fixed (tj

i) – scanner is bottleneck

  • Buffer modules may be placed only just before the bottleneck (scanner)
  • Setups may be required between wafers of different types
  • Wafer may have a maximum allowed residency time in each module

(time window: [tj

i, tj i + rj i] ) – process is a success if this is obeyed

  • Objective(s):
  • Maximize steady-state throughput
  • Minimize the effect of disturbances on throughput (“non steady-state”)
  • Minimize variation in module residence times for like wafers
slide-10
SLIDE 10

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 10

Axiomatic Design at the System Level (2)

Functional Requirements:

  • FR1. Conduct wafer processes

to exceed bottleneck rate (lB)

  • FR2. Transport wafers

(physically + orchestration)

Design Parameters:

  • DP1. Process modules
  • DP2. Robots and algorithms

                   2 1 2 1 DP DP X X X FR FR

Decoupled design

X = Relationship between DP and FR 0 = Negligible relation between DP and FR

[1] Axiomatic Design: Advances and Applications, Nam Pyo Suh, Oxford University Press, 2001

So long as our robots/algorithms obey the process time windows, this will remain 0!

slide-11
SLIDE 11

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 11

Axiomatic Design at the System Level (3)

Functional Requirements:

  • FR1.1. Position, enter/exit wafers
  • FR1.2. Conduct process
  • FR1.2.1. Prepare for process
  • FR1.2.2. Maintain process quality
  • FR1.2.3. Conduct process
  • FR1.2.4. Ensure process rate (<lB)
  • FR2.1. Physically move wafers
  • FR2.2. Orchestrate steady state

(SS) operation

  • FR2.2.1. Decouple SS process times
  • FR2.2.2. Minimize SS wait to transport
  • FR2.3. Orchestrate transient
  • peration

Design Parameters:

  • DP1.1. Method for positioning
  • DP1.2. System for processing
  • DP1.2.1. Recipe setup system
  • FR1.2.2. Module cleaning system
  • FR1.2.3. Process modules
  • FR1.2.4. Sufficient number of modules
  • DP2.1. Robots
  • DP2.2. Algorithms for steady state

(SS) operation

  • DP2.2.1. Cyclic schedule
  • DP2.2.2. Algorithm to minimize waiting
  • DP2.3. Algorithms/structure for

transient operation

slide-12
SLIDE 12

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 12

Axiomatic Design at the System Level (4)

Functional Requirements:

  • FR 2.3. Orchestrate transient
  • peration
  • FR2.3.1. Reestablish SS
  • FR2.3.2. Protect from disturbance
  • FR2.3.3. Recover time lost due to

disturbance

  • FR2.3.4. Maintain decoupling for

wafers not delayed by disturbance

  • FR2.3.5. Decouple and minimize

transient wafer residency times

  • FR2.3.6. Replenish protection from

delay

Design Parameters:

  • DP 2.3. Algorithms/structure for

transient operation

  • DP2.3.1. Algorithm to return to SS
  • DP2.3.2. Buffer before the bottleneck
  • DP2.3.3. Algorithm to minimize distance

between normal/disturbed wafers

  • DP2.3.4. Same SS cyclic schedule for

wafers not disturbed

  • DP2.3.5. Algorithm to decouple and

minimize delayed wafers

  • DP2.3.6. Wafer input rate to tool

(= process rate of prescan bottleneck)

slide-13
SLIDE 13

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 13

Axiomatic Design at the System Level (5)

  • Concepts of the design (design parameters)

Scan

DP2.3.4. Same SS cyclic schedule for wafers downstream of(after) disturbance DP2.3.2. Buffer DP2.3.3. Minimum distance between delayed/normal wafers DP2.3.5. Decouple transient transport DP2.3.6. Input rate DP2.3.1. Algorithm to return all wafers to SS cyclic schedule

slide-14
SLIDE 14

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 14

Axiomatic Design at the System Level (6)

  • Design matrix for the transient operation

                                                             6 . 3 . 2 5 . 3 . 2 4 . 3 . 2 3 . 3 . 2 2 . 3 . 2 1 . 3 . 2 6 . 3 . 2 5 . 3 . 2 4 . 3 . 2 3 . 3 . 2 2 . 3 . 2 1 . 3 . 2 DP DP DP DP DP DP X X X X X X X X FR FR FR FR FR FR

Decoupled design

X = Relationship between DP and FR 0 = Negligible relation between DP and FR

Note: The entire design matrix is decoupled

Return to SS Protect Recover Preserve SS Decouple transient Replenish Algorithm Buffer Algorithm Same cycle Algorithm Input rate

slide-15
SLIDE 15

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 15

Axiomatic Design at the System Level (7)

  • Relationship between design parameters our objectives

Design Parameters:

  • DP2.3.1. Algorithm to return to SS
  • DP2.3.2. Buffer before the

bottleneck

  • DP2.3.3. Algorithm to minimize

distance between normal/disturbed wafers

  • DP2.3.4. Same SS cyclic schedule

for wafers not disturbed

  • DP2.3.5. Algorithm to decouple

and minimize residency times

  • DP2.3.6. Wafer input rate to tool

(= process rate of prescan bottleneck)

Objective Functions:

  • Maximize steady-state

throughput

  • Minimize the effect of

disturbances on throughput

  • Minimize variation in module

residence times for like wafers

slide-16
SLIDE 16

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 16

Axiomatic Design at the System Level (8)

  • The flavor of the algorithms: Subset of DP2.3.3.
  • Algorithm to minimize disturbance due to different wafer classes
  • Let x(i,j) = start time in module i for wafer j
  • Let c(i,j) = completion time from module i of wafer j
  • Minimize the time between wafer exits from the tool
  • Guarantee similar wafers experience same module residency times
  • Equivalent formulation as a mathematical program:

     

 

           

     1 1 1 1 ,..., 2

1 , 1 , 1 , 1 max , 1

m k j m j k j k M m

t t t j x j c j x

     

 

M m t t t j x j x j x

m k j m j k j k

,..., 1 , 1 , 1 , 1 subject to , 1 min

1 1 1 1

     

   

slide-17
SLIDE 17

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 17

Presentation Overview

  • Part I: Design of stochastic systems
  • System description: Photolithography clusters in computer chip

fabrication

  • Why does a system-level and stochastic perspective matter?
  • Design for throughput
  • Part II: Design of service systems
  • Port system decoupling leads to service concept
  • Concluding remarks
slide-18
SLIDE 18

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 18

Port Service Systems and Decoupling (1)

  • Goal: Design port service systems
  • Method: Axiomatic design
  • Functional Requirements (subset): Port service
  • Unload goods from input carrier
  • Load goods to output carrier
  • Transfer incoming goods from sea to land
  • Transfer outgoing goods from land to sea
  • To maintain the independence of these requirements:
  • Mobile floating port (MFP) or “mobile harbor”
slide-19
SLIDE 19

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 19

Port Service Systems and Decoupling (2)

  • Typical interpretation of “Transfer goods from sea to land”
  • Porting service should be directly tied to a specific land-based port
  • This interpretation is not solution neutral!
  • Independence of MFP from its nominal land port
  • Design MFP to be relatively small and agile
  • Decoupling from the land based port entirely allows MFP to:
  • Serve congested ports world-wide
  • Provide a genuine port service!
slide-20
SLIDE 20

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 20

Presentation Overview

  • Part I: Design of stochastic systems
  • System description: Photolithography clusters in computer chip

fabrication

  • Why does a system-level and stochastic perspective matter?
  • Design for throughput
  • Part II: Design of service systems
  • Port system decoupling leads to service concept
  • Concluding remarks
slide-21
SLIDE 21

2nd KI International Symposium – Daejeon, South Korea – September 4, 2008 – 21

Concluding Remarks

  • Part I: Design of stochastic systems
  • System perspective on the design of photolithography clusters
  • Such disturbances can/often play a dominant role in performance!
  • Design can allow numerous objective functions
  • Next steps: Conclude algorithm design and quantify performance
  • Part II: Design of service systems
  • Port system decoupling leads to service concept
  • Next Steps: Continued service perspective within the Axiomatic

Design framework