On the Throughput of Clustered Photolithography Tools: Wafer - - PowerPoint PPT Presentation

On the Throughput of Clustered Photolithography Tools:

Wafer Advancement and Intrinsic Equipment Loss Maruthi Kumar Mutnuri James R. Morrison, Ph.D.

September 23, 2007

2

Presentation Outline

 Motivation  Model 1: Synchronous photolithography model

 System Description  Time between lot completions with diverse lot populations  Time between lot completions with same class of lots

 Model 2: Asynchronous photolithography model

 System Description  Wafer completion times with a single class of lots  Intrinsic equipment loss:

 Reticle change (as a pause in the bottleneck module)

 Concluding remarks

3

Motivation

 Goal: One generic model for all classes of serial processing cluster

tools

 Abstract models useful for clustered photolithography tools

 Movement of individual wafers can be analyzed  Module level rather than conventional tool level approach

 Contribution to flow line literature

 High fidelity models with direct application to fabricator simulation  A new class of failures – setup dependent upon state of system  Simplified recursions for system evolution

4

Synchronous Photolithography Model: System Description

 Wafers can only advance at the same instant as all others in the

tool – their movement is synchronized

 Process time in module mj for family F lots is DF

j

 May be 0 to model a buffer (only useful for module failure analysis)

 Let k(i) denote the number of empty modules in advance of lot li

Lots may have different deterministic process times in a module Robot

m1 m2 m3 m4 m5 m6 m7 m8 m15 m14 m13 m12 m11 m10 m9

W wafers/lot M modules

5

Synchronous Photolithography Model: Wafer Advancement

 Rate of wafer advance is dictated by the maximum

module time for all occupied modules

 For lot li with family F(i), define the effective module

process time as

 The slowest possible effective process time is

   

 

i F i F r M r q p r r q p

D  

   

max

}

• r

1 : { ,

   

i F i F j j

D   max

m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m14

6

Synchronous Photolithography Model:

Lot Completion for Diverse Lot Populations

 There are two families of lots  Time between the departure of the previous lot and

departure of lot li may be calculated as:

 

) , max( ) 1 (

) 1 ( 2 ) 1 ( ) ( , ) 1 ( 1 ) ( , ) ( 1 ) ( ) ( 1 ,

1 , ) 1 ( 1

  

         

   

          

M i k j i F i F j i k j i F j i F M i k M j i F M j i

M i k j

M W T

Time for first wafer to reach last module

Here, for notational simplicity, we assume that at most two lots can be on the tool at any instant

Time for last wafer to exit first module Time until first wafer of lot li+1 enters tool Time until last wafer exits the tool

7

Synchronous Photolithography Model:

Lot Completion for Uniform Lot Population

 Lots are of same family  Time between the departure of the previous lot and

departure of lot li may be calculated as:

 

  

           

         

M i k j j i k j i k j j M i k M j M j i

M W T

) 1 ( 2 , ) 1 ( 1 ) 1 ( 1 , 1 ) ( 1 ,

) 1 (

Time for first wafer to reach last module

Here, for notational simplicity, we assume that at most two lots can be on the tool at any instant

Time for last wafer to exit first module Time until first wafer of lot li+1 enters tool Time until last wafer exits the tool

8

Synchronous Photolithography Model: Example

Parameters: M=11 and W=10

Process Times D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Family F1 20 25 40 35 30 50 15 35 45 20 30 Family F2 30 35 50 45 40 60 25 45 55 30 40 Time between lot completions, Ti

550 600 650 700 750 800 850 900 1 2 3 4 5 6 7 8 9 10

• No. of Empty Modules, Ki=Ki+1

Time between lot completions, Ti

9

Asynchronous Photolithography Model: System Description

 Assume that all wafers in the tool advance at their own rate so

long as there are module locations available to do so

 Process time in module mj for all lots is Dj

 May be 0 to model a buffer  Only one class of lots (can readily model many classes but requires

full simulation approach)

m1 m2 m3 m4 m5 m6 m7 m8 m15 m14 m13 m12 m11 m10 m9

W wafers/lot M modules Lots are of same class, but may have different size

10

Asynchronous Photolithography Model: Parameters

 Number of modules in the cluster:

M

 Process time for a wafer in module m:

Dm

 Largest (bottleneck) process time:



 Number of wafers per lot

W

 Denote the i-th lot:

li

 Arrival time of lot li:

ai

m1 m2 m3 m4 m5 m6 m7 m8 m15 m14 m13 m12 m11 m10 m9

W wafers/lot M modules Lots are of same class, but may have different size

Includes buffers Can easily generalize to depend upon the lot

11

Asynchronous Photolithography Model: Wafer Advancement

 The evolution equations for the system may be written

 Let xj(w) denote the entry time of wafer w to module mj,  At the first module:  For the intermediate modules (2 ≤ w ≤ M-1):  For the last module:

     

1 , max

2 1

  w x a w x

w

     

 

1 , max

1 1 1

 D  

  

w x w x w x

j j j j

     

 

M M M M M

w x w x w x D   D  

 

1 , max

1 1

,

12

Asynchronous Photolithography Model: Towards Completion Time

 The completion Ci time of lot li is dictated by two

possibilities:

 Case i: Lot li arrives early enough so that its wafers

begin to exit immediately after those of lot li-1

 Case ii: Lot li arrives so late that it does not run into lot

li-1 in front of it

  



W C C

i i 1

One wafer exits every  units of time

 

  D  





1

1

W a C

M j j i i

Remaining wafers exit every  units

• f time

First wafer exits

13

Asynchronous Photolithography Model: Completion time

 The completion C(i) time of lot li obeys the following recursion:

  



    D  



1 , max

1

W C e a C

i T i i

   

M i 1 , max , , m module in a wafer

• f

time Processing track the in modules

• f

Number M

i 1

  D   D D  D  D 

T M m



 

  D   1 W e a C

T i i

with initial condition (for an empty tool) where Proof: Start with the max-plus algebra representation of the evolution equations and employ an induction within an induction

 

T

e a 1 , , 1 system the to i lot

• f

time Arrival lot a in wafers

• f

Number W

i

   

14

Asynchronous Photolithography Model: Example 1

 Example: M = 5, W = 3,  = 50 sec

 

140 30 ) 1 3 ( 80 1

1 1

        D   W e a C

T

  

    

230 60 170 , 165 max ) 30 )( 2 ( 30 140 , 80 85 max 1 , max

1 2 2

            D   W C e a C

T

Process Time 15 Module 5 1 1 1 2 2 2 3 3 3 1 1 1 2 2 2 3 3 3

30

Module 4 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 Module 3 2 2 3 3 3 3 1 2 2 2 3 3 3 3 3 15 Module 2 1 1 1 2 2 2 3 3 3 1 1 1 2 2 2 3 3 3 20 Module 1 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2 2 2 2 3 3 3 3 25 50 75 100 125 150 175 200 225 L1 enters system at time a1 = 0 L1 exits system at time c1 = 140 L2 enters system at time a2 = 85 L2 exits system at time c2 = 230

No time lost on the bottleneck!

15

Asynchronous Photolithography Model: Example 2

 Example: M = 5, W = 3,  = 50 sec

 

140 30 ) 1 3 ( 80 1

1 1

        D   W e a C

T

  

    

240 60 170 , 180 max ) 30 )( 2 ( 30 140 , 80 100 max 1 , max

1 2 2

            D   W C e a C

T

Process Time 15 Module 5 1 1 1 2 2 2 3 3 3 1 1 1 2 2 2 3 3 3

30

Module 4 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 Module 3 2 2 3 3 3 3 2 2 3 3 3 3 15 Module 2 1 1 1 2 2 2 3 3 3 1 1 1 2 2 2 3 3 3 20 Module 1 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2 2 2 2 3 3 3 3 25 50 75 100 125 150 175 200 225 L1 enters system at time a1 = 0 L1 exits system at time c1 = 140 L2 enters system at time a2 = 100 L2 exits system at time c2 = 240

10 seconds lost on the bottleneck!

16

Asynchronous Photolithography Model: One class of Intrinsic Equipment Loss

 If the bottleneck module fails (pauses), a recursion for the

completion time of lots may be found

 Time of the r-th pause:

tR(r)

 Duration of the r-th pause:

dR(r)  The first lot which may be delayed by the pause has the smallest

lot index satisfying

  



 

 

r W c e a

R M B j j i T i

t  D       D 



   1 1

1 , max

Completion time of the lot had there been no pause Time after exiting the bottleneck

Departure time from the bottleneck if no pause

17

Asynchronous Photolithography Model: Completion time with Loss

 Adjust the completion time of the first possibly delayed lot

(otherwise use the standard recursion)

 Can be used to model reticle change events

 

i i i

g C C , max

0 



  



    D  



1 , max

1

W c e a C

i T i i

     

       D     



  i M B j j R R R i

f W r d r r d g

1

, min t

where Original completion time of the lot Delay incurred

18

Asynchronous Photolithography Model: Example with Loss

 Example: M = 5, W = 3,  = 50 sec, tR(r)=95, dR(r)=15

             

155 15 , max 140 , max 15 75 , 15 min , min 140 30 ) 1 3 ( 80 1

1 1 1 1 1 1 1 1

              D              D  



 

g f C f W r d r r d g W e a f

M B j j R R R T

t

  

    

245 60 185 , 180 max ) 30 )( 2 ( 30 155 , 80 100 max 1 , max

1 2 2

            D   W C e a C

T

Proces s Time 15 Module 5 1 1 1 2 2 2 3 3 3 1 1 1 2 2 2 3 3 3

30

Module 4 1 1 1 1 1 1 2 2 2 2 2 2 R R R 3 3 3 3 3 3 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 Module 3 2 2 3 3 3 3 1 2 2 2 3 3 3 3 3 15 Module 2 1 1 1 2 2 2 3 3 3 1 1 1 2 2 2 3 3 3 20 Module 1 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2 2 2 2 3 3 3 3 25 50 75 ## ## ## ## ## ## Reticle Change at time t R(r) = 0 L1 enters system at time a1 = 0 L1 exits system at time c1 = 155 L2 enters system at time a2 = 100 L2 exits system at time c2 = 245

Reticle change

19

Concluding Remarks

 Synchronous model

 Realistic manufacturing system – single robot transfers the wafers  K can be used to model intrinsic equipment losses such as

 Complete tool failure  Late lot arrival  Setup change

 Asynchronous model

 “Ideal” manufacturing system with efficient wafer transport system

 Future work

 Synchronous model of generic arrivals, reticle change and setup change  Asynchronous model with setup times  Compare performance between models with real data  Incorporate into fab simulation  Recommend operational design principles