Section 3 Section 3 Number Formats and Registers a 3-1 1
Binary Number Formatting a 3-2 2
Binary Notation in DSP's The ADSP-BF533 is a fixed point processor that performs operations using a two's complement binary notation. Therefore, to efficiently program a DSP it is important to understand the following concepts: 1) Signed vs Unsigned formats 2) Fractional vs Integer formats 3) Ranges of Fractional Numbers While the Blackfin Processor does process 8, 16 and 32 bit data, only 16-bit examples are shown in this section for brevity. a 3-3 3
Binary - Hexadecimal - Decimal Number Conversion Table Decimal Hexadecimal Binary 0 0 0000 1 1 0001 2 2 0010 3 3 0011 4 4 0100 5 5 0101 6 6 0110 7 7 0111 8 8 1000 9 9 1001 10 A 1010 11 B 1011 12 C 1100 13 D 1101 14 E 1110 15 F 1111 a 3-4 4
Example of Data Formats 16 Bits of Data S/U U U U U U U U U U U U U U U U 0 15 Binary Bit Pattern Example System 0x0000 0V (- FULL SCALE) Unsigned 0xFFFF 5V (+ FULL SCALE) 0x8000 -5V (- FULL SCALE) Signed 0x0000 0V 0x7FFF 5V (+ FULL SCALE) a 3-5 5
2's Complement Representation In 2's complement representation, the bit weight of the sign bit (MSB) of a number is seen as -(2)^(M-1) where M is the number of bits left of the binary point. For a 4.2 number, the sign scale is -(2^3). 3 -2 2 1 0 -1 -(2 ) 2 2 2 • 2 2 Sign Bit Binary Point Sign Bit Binary Point Example: 0101.01 = 0 * (-8) + 1 * (4) + 0 * (2) + 1 * (1) + 0 * (1/2) + 1 * (1/4) = 5.25 1101.01 = 1 * (-8) + 1 * (4) + 0 * (2) + 1 * (1) + 0 * (1/2) + 1 * (1/4) = - 8 + 5.25 = - 2.75 a 3-6 6
2's Complement Representation Changing the sign of a 2‘s Complement Number -X = NOT(X) + 1 LSB ( invert all the bits and add an LSB) Example: -5.25 = -(b#0101.01) = NOT(b#0101.01) + b#0000.01 = b#1010.10 + b#0000.01 = b#1010.11 1010.11 = 1 * (-8) + 0 * (4) + 1 * (2) + 0 * (1) + 1 * (1/2) + 1 * (1/4) = - 8 + 2.75 = - 5.25 a 3-7 7
Fractional versus Integer Notation • Fractional format is 1.15 notation S F F F F F F F F F F F F F F F • radix point • Integer format is 16.0 notation S I I I I I I I I I I I I I I I • radix point a 3-8 8
DSP is optimized for fractional notation DSP supports integer notation a 3-9 9
Ranges for 16 bit Formats FORMAT Largest Positive Largest Negative Value of 1 LSB Value (0x7FFF) Value (0x8000) (0x0001) In Decimal In Decimal In Decimal 1.15 0.999969482421875 –1.0 0.000030517578125 Fractional 2.14 1.999938964843750 –2.0 0.000061035156250 3.13 3.999877929687500 –4.0 0.000122070312500 4.12 7.999755859375000 –8.0 0.000244140625000 5.11 15.999511718750000 –16.0 0.000488281250000 6.10 31.999023437500000 –32.0 0.000976562500000 7.9 63.998046875000000 –64.0 0.001953125000000 8.8 127.996093750000000 –128.0 0.003906250000000 9.7 255.992187500000000 –256.0 0.007812500000000 10.6 511.984375000000000 –512.0 0.015625000000000 11.5 1023.968750000000000 –1024.0 0.031250000000000 12.4 2047.937500000000000 –2048.0 0.062500000000000 13.3 4095.875000000000000 –4096.0 0.125000000000000 14.2 8191.750000000000000 –8192.0 0.250000000000000 15.1 16383.500000000000000 –16384.0 0.500000000000000 16.0 Integer 32767.000000000000000 –32768.0 1.000000000000000 a 3-10 10
Format Example +5 V 0x7FFF 1 2 0 V 0x0000 3 4 5 -5 V 0x8000 FORMAT 16.0 1.15 1) 0x7FFF = 32767 -> 5 V 0.999969482... -> 5 V 2) 0x3FFF = 16383 -> 2.5 V 0.499969482... -> 2.5 V = 0 -> 0 V 0.0000000... -> 0 V 3) 0x0000 4) 0xCCCD = -13107 -> -2.0 V -0.399993986... -> -2.0 V 5) 0x8000 = -32768 -> -5.0 V -1.0000000.... -> -5.0 V a 3-11 11
Registers and Register File a 3-12 12
Accessing Registers Accessing Registers • Blackfin Processors are register-intensive devices − All computations are performed on data contained in registers − All peripherals are setup using registers − Memory is accessed using pointers in address registers • There are two ways to access registers on the ADSP-BF533 − Directly by name − Memory-mapped registers (MMRs) a 3-13 13
ADSP- -BF533 Core Registers BF533 Core Registers ADSP • Core registers accessed by name − Data Registers: R0-R7 − Accumulator Registers: A0, A1 − Pointer Registers: P0-P5, FP, SP,USP − DAG Registers: I0-I3, M0-M3, B0-B3, L0-L3 − Cycle Counters: Cycles, cycles2 − Program Sequencer: SEQSTAT − System Configuration Register: SYSCFG − Loop Registers: LT[1:0], LB[1:0], LC[1:0] − Interrupt Return Registers: RETI, RETX, RETN, RETE Example: R0 = SYSCFG; // Load data register with contents of SYSCFG register a 3-14 14
Core Registers Core Registers 0 31 Data Registers P0 Address Data Registers: 31 15 P1 Pointer Registers: R0-R7 are Registers A0.H A0.L A0X P2 referred to as P0-P5 are referred A1.H A0.L A1X P3 to as “preg” “dreg” P4 31 15 R0 R0.H R0.L P5 _lo refers to .L R1 R1.H R1.L FP and R2 SP R3 USP _hi refers to .H R4.H R4.L R4 31 0 31 0 31 0 31 0 R5 I0 L0 B0 M0 Index Registers: R6 I1 L1 B1 M1 I0-I3 are referred I2 L2 B2 M2 R7 R7.H R7.L to as “ireg” I3 L3 B3 M3 Loop Counter Arithmetic Status ASTAT LC0 LT0 Loop Top Shaded registers LB0 Loop Bottom only accessible in Subroutine Return RETS Supervisor mode Interrupt Return LC1 RETI LT1 Exception Return RETX LB1 NMI Return RETN SYSCFG System Config Emulation Return RETE SEQSTAT Sequencer Status a 3-15 15
Memory Mapped Registers (MMRs MMRs) ) Memory Mapped Registers ( • A majority of registers are memory mapped and must be accessed indirectly − Core MMRs are used to configure the core registers • They are listed in Appendix A of the HRM • All Core MMRs must be accessed with 32-bit reads or writes − System MMRs are used to configure all other peripherals • They are listed in Appendix B of the HRM • Some System MMRs must be accessed with 32-bit reads or writes and others with 16-bit reads or writes (See the HRM for details) • The addresses of the core and system MMRs are defined in the defBF533.h, defBF532.h, defBF531.h and defLPblkfin.h header files • MMRs can only be accessed in Supervisor mode Example: P0.H = hi(MMR_NAME); // load upper 16-bits of MMR address to address register P0.L = lo(MMR_NAME); // load lower 16-bits of MMR address to address register R0 = w[P0] (z); // load data register with contents of MMR a 3-16 16
ADSP- -BF533 Register Groups BF533 Register Groups ADSP • Core Memory-mapped Registers − L1 Data Memory Registers − L1 Instruction Memory Registers − Core Timer Registers − Core Interrupt Controller Registers − Debug Registers • System Memory-mapped Registers − Watchdog Timer Registers − Timer Registers − RTC Registers − PPI Registers − EBIU Registers − GPIO Registers (Programmable flags) − UART Registers − SPORT Registers − SPI Registers − DMA Registers − PLL Registers a 3-17 17
ADSP-BF533 Block Diagram L1 Core Instruction Timer 64 Memory Performance Core LD0 32 Monitor Processor L1 Data LD1 32 Memory JTAG/ Debug SD32 Core D0 bus Core I bus DMA Mastered 32 Core DA0 bus Core D1 bus Core DA1 bus 64 32 32 32 32 bus Core Clock (CCLK) Domain CORE/SYSTEM BUS INTERFACE System Clock (SCLK) Domain 16 DMA Core Bus (DCB) 16 Data Watchdog Event Power DMA Controller EBIU Address Real Time Clock 16 And Timers Controller Management Control DMA Ext Bus External Port Bus (DEB) (EPB) 16 16 16 Peripheral Access Bus (PAB) DMA Access Bus (DAB) External Access Bus (EAB) Programmable UART0 1KB internal SPORTs SPI PPI flags IRDA Boot ROM a 3-18 18
ADSP- -BF533 Core BF533 Core ADSP Addressing Arithmetic Unit Addressing Arithmetic Unit Data Arithmetic Unit Data Arithmetic Unit FP FP SP SP P5 P5 P4 P4 16 16 16 16 I3 I3 L3 L3 B3 B3 M3 M3 P3 P3 8 8 8 8 8 8 8 8 I2 I2 L2 L2 B2 B2 M2 M2 P2 P2 R7 R7 I1 I1 L1 L1 B1 B1 M1 M1 P1 P1 R6 R6 B0 B0 M0 M0 I0 I0 L0 L0 DAG0 DAG0 DAG1 DAG1 P0 P0 R5 R5 R4 R4 barrel barrel 40 40 40 40 shifter shifter R3 R3 R2 R2 R1 R1 acc0 acc0 acc1 acc1 R0 R0 LD0 LD0 32 32 Memory Memory LD1 LD1 32 32 Management Management Core Registers Core Registers Core Registers DA0 DA0 DA1 DA1 SD SD 32 32 32 32 32 32 LC0 LC0 LC0 LT0 LT0 LT0 LB0 LB0 LB0 Program Program LC1 LC1 LC1 LT1 LT1 LT1 LB1 LB1 LB1 32 32 IAB IAB Dcache/SRAM Dcache/SRAM 4KB SRAM 4KB SRAM L1 Instruction Memory L1 Instruction Memory Sequencer Sequencer ASTAT ASTAT ASTAT RETS RETS RETS 64 64 IDB IDB SRAM/Cache SRAM/Cache SYSCFG SYSCFG SYSCFG RETI RETI RETI L1 Data Memory L1 Data Memory SEQSTAT SEQSTAT SEQSTAT RETX RETX RETX RETN RETN RETN Core D0 bus Core D0 bus Core I bus Core I bus 32 32 64 64 32 32 RETF RETF RETF Core D1 bus Core D1 bus System Bus Interface Unit System Bus Interface Unit a 3-19 19
Register File Register File a 3-20 20
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