Digital Systems 00/100 00/0-- 00/0-- A B F to state A 01/0-- - - PowerPoint PPT Presentation

Digital Systems

Calcolatori Elettronici e Sistemi Operativi

MAX-3

A B

C

D

E

00/0-- 01/0-- 10/0-- 11/0--

F G

H

I

00/0-- 01/0-- 10/0-- 11/0-- 00/100 01/101 10/110 11/111 to state A to state A to state A to state A 00/0-- 01/0-- 2/0-

Maximum among 3 numbers 2-bit wide Outputs:

DONE (1 bit) DATA (2 bit)

MAX-3

Too many states for practical cases, even if the algorithm is quite simple Partition between data and control

Maximum among 3 numbers 2-bit wide Outputs:

DONE (1 bit) DATA (2 bit)

Mealy: 9 states Moore: 13 states MAX-k for numbers n-bit wide? Mealy: 1 + (k-1) · 2n Moore: 1 + k · 2n

Digital system

Flip Flop and logic gates Modeled as a FSM

Complex system

Huge number of states Intractable

Partitioning

Functional blocks

Registers - Counters - Decoder - Multiplexer - Bus - Arithmetic units - Flip flop - Logic gates

Partitioning

Datapath

Operations on data

Control Unit

Control signals

To drive the datapath

Status signals

The control unit varies the flow of the algorithm Control Unit Control Unit Datapath Datapath

Control Signals Status Signals Control Inputs Control Outputs Data Inputs Data Outputs

Max-3

REG

>

OUT MAJ CLK STORE IN

n n n

n

A B 0/01 1/01 C 0/00 1/01 0/10 1/11

CTRL-Unit Datapath

OUT DONE IN STORE MAJ

Input: MAJ Outputs: DONE, STORE

Datapath

Calcolatori Elettronici e Sistemi Operativi

Datapath

Registers

Basic components: memory elements Operations on data stored in registers

Register Transfer operations Description at “Register Transfer Level” (RTL)

RTL Description

Registers set Available operations on data stored in registers Controller that manages the execution flow

n-bit register

1 2 n-1

D D D

n n

load load

Register

Requirements:

Component that stores data for unlimited clock cycles The store operation is regulated by a dedicated control signal (load)

load=1 store input data load=0 keep the data already stored

Basic block:

Flip flop D (with load input) Flip flop D (without load input)

Stores data at each clock cycle Use a gate to mask the flip-flop's clock (clock-gating) Store in the register its own output (feedback)

Register

D

IN OUT load CLK

D

IN OUT load CLK

M U X

Simple Timing issues:

Logic gate on the clock tree Requirement: load 0 1 only when clk=0

No timing issues A multiplexer is needed D

IN OUT load CLK

Notation

Identifier with only uppercase letters and numbers: registers R0, R1, ... , IR Parentheses: register or signal portion R2(1) : bit 1 of register R2 R3(3:0) : the 4 least significant bits of R3 Square brackets: memory (or register bank) reference M[0x100] : memory location at address 0x100 M[R1] : memory location at address indicated by R1 REGS[12]: register 12 in a register bank called REGS

Operations

• peration

symbol VHDL equivalent combinatorial assignment <- <= data transfer between registers <= <= sum + + subtraction

• bitwise AND ∧

and bitwise OR ∨

• r

bitwise XOR ⊕ xor bitwise NOT  not left shift sl sll right shift sr srl portion of data A(3:0) A(3 downto 0) data concatenation || &

Examples: R0 <= R1 + R2

• ut <- R1 + R2 + 1

R1 <= R1 + 1 No multiply and division

RTL operations

Actions to transfer the value stored in a register in another register

Example: R0 <= R1 load R0 with the content of R1

Arithmetic operations

Sum, Subtraction, Increment, Decrement, Complement

Implemented by arithmetic circuits

Usually, subtractions are implemented through an adder (2- complement) Increment and decrement, are often implemented using specialized hardware (improved efficiency)

The operation involves the whole register content

Arithmetic operations

Sum, Subtraction, Increment, Decrement, Complement

Examples: R0 <= R1+R2 sum of the content of two registers R0 <= R1 1-complement R0 <= R1+1 2-complement R0 <= -R1 2-complement R0 <= R1+1 increment R0 <= R1-1 decrement R0 <-= R1+R2+1 subtraction (through an adder and 2-complement) R0 <-= R1-R2 subtraction (through an adder and 2-complement)

Logical operations

Operations on individual bits of a register

and, or, xor, not, ...

0 1 1 0 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 0 0 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 1 1 0 1 0 0 1 1

and = example: R1 ∧ R2 R1 R2

Shift Operations

Shift of the register content

0 1 1 0 0 0 1 1 1 0 1 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 1 1 0 0 0 1

example: left shift of 2 bits R1 R1

Sometimes the last bit “dropped” by the register is stored in another flip-flop. Bits “entering” in the register

left shift: always 0 right shift logical shift: 0 arithmetic shift aritmetico: equal to the most significant bit (MSB) of the register

RT structures

Example 1:

Operations to be performed: A+B and C+D Not concurrently (not in the same cycle) share adder

+

A C B D sel1 sel2 sel1 , sel2: control signals

(form the ctrl-unit) n n n n n n n

RT structures

Example 2:

Operations to be performed: R <= A , R <= X+Y

+

A X Y sel load sel , load: control signals

(from the ctrl-unit)

R

n n n n

RT structures

A load1 R1 load2 R2 load3 R3

n Eventually encoded (thus, using a decoder in datapath)

Example 3:

Operations to be performed: R1 <= A , R2 <= A , R3 <= A

load1 , load2 , load3: control signals

(from the ctrl-unit)

DECO load

2

RT structures

Registers can receive input data from more sources

Multiplexer

Input data are selected through a multiplexer

Bus

A single multiplexer drives a bus which is input of more registers

Tri-state bus

The bus is driven by tri-state buffers

Other:

Several multiplexer More buses Composition of different structures

RT through bus

Available transfers: all Source and destination are selected through signals S and D

Di Sj : Ri <- Rj

R0

LOAD

M U X

n

S0 S1

R1

LOAD

R2

LOAD S2 D0 D1 D2 S0 S1 S2

n n n n n n bus

RT through tri-state bus

R0

LOAD

R1

LOAD

R2

LOAD D2 D1 D0

n n n n n bus n n n n

S0 S1 S2

Available transfers: all Source and destination are selected through signals S and D

Di Sj : Ri <- Rj

R0

L

R1

L

R2

L D2 D1 D0

bus n n n

S0 S1 S2

R

LOAD

n

EN

n

LOAD

R

L

n

EN LOAD E E E E

RT through tri-state bus

Available transfers: all Source and destination are selected through signals S and D

Di Sj : Ri <- Rj