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❚✐♠❡❞ ●❛♠❡s ❢♦r ❈♦♠♣✉t✐♥❣ ❲❈❊❚ ♦♥ P✐♣❡❧✐♥❡❞ Pr♦❝❡ss♦rs ✇✐t❤ ❈❛❝❤❡s ❋r❛♥❝❦ ❈❛ss❡③ ❈◆❘❙ ✫ ▼❛r✐❡ ❈✉r✐❡ ❋❡❧❧♦✇ ■❘❈❈②◆✱ ◆❛♥t❡s✱ ❋r❛♥❝❡ ❏✉♥❡ ✷✹t❤✱ ✷✵✶✶ ❆❈❙❉✬✷✵✶✶✱ ◆❡✇❝❛st❧❡✱ ❯❑

❖✉t❧✐♥❡ ♦❢ t❤❡ t❛❧❦ ❚❤❡ ❲♦rst✲❈❛s❡ ❊①❡❝✉t✐♦♥✲❚✐♠❡ Pr♦❜❧❡♠ ✶ ▼♦❞✉❧❛r ❈♦♠♣✉t❛t✐♦♥ ♦❢ ❲❈❊❚ ✷ ❊①♣❡r✐♠❡♥ts ✫ ❘❡s✉❧ts ✸ ❈♦♥❝❧✉s✐♦♥ ✫ ❋✉t✉r❡ ❲♦r❦ ✹

❲♦rst✲❈❛s❡ ❊①❡❝✉t✐♦♥✲❚✐♠❡ 10: e3a03000 mov r3, #0 14: e58d3014 str r3, [sp, #20] 18: e3a03002 mov r3, #2 1c: e58d300c str r3, [sp, #12] 20: ea00000a b 50 <fib+0x50> 24: e59d3010 ldr r3, [sp, #16] 28: e58d3018 str r3, [sp, #24] 2c: e59d2010 ldr r2, [sp, #16] 30: e59d3014 ldr r3, [sp, #20] Pr♦❣r❛♠ P add 34: e0823003 r3, r2, r3 38: e58d3010 str r3, [sp, #16] ldr 3c: e59d3018 r3, [sp, #24] 40: e58d3014 str r3, [sp, #20] ldr 44: e59d300c r3, [sp, #12] 48: e2833001 add r3, r3, #1 4c: e58d300c str r3, [sp, #12] 50: e59d200c ldr r2, [sp, #12] 54: e59d3004 ldr r3, [sp, #4] 58: e1520003 cmp r2, r3 5c: dafffff0 ble 24 <fib+0x24> 60: e59d3010 ldr r3, [sp, #16] ■♥♣✉t ❞❛t❛ t✐♠❡✭ ❍❀ P❀ ❞ ✮ ❞ ∈ D R13 R13 Inst. Data ARM9TDMI Cache Core Cache Coprocessor 15 ❍❛r❞✇❛r❡ ❍ Data Inst. MMU MMU Write Buffer AMBA bus interface ❆❈❙❉✬✷✵✶✶ ✭◆❡✇❝❛st❧❡✱ ❯❑✱ ❏✉♥❡ ✷✵✶✶✮ ❚✐♠❡❞ ●❛♠❡s ❢♦r ❈♦♠♣✉t✐♥❣ ❲❈❊❚ ✶ ✴ ✷✷

❲♦rst✲❈❛s❡ ❊①❡❝✉t✐♦♥✲❚✐♠❡ 10: e3a03000 mov r3, #0 14: e58d3014 str r3, [sp, #20] 18: e3a03002 mov r3, #2 1c: e58d300c str r3, [sp, #12] 20: ea00000a b 50 <fib+0x50> 24: e59d3010 ldr r3, [sp, #16] 28: e58d3018 str r3, [sp, #24] 2c: e59d2010 ldr r2, [sp, #16] 30: e59d3014 ldr r3, [sp, #20] Pr♦❣r❛♠ P add 34: e0823003 r3, r2, r3 38: e58d3010 str r3, [sp, #16] ldr 3c: e59d3018 r3, [sp, #24] 40: e58d3014 str r3, [sp, #20] ldr 44: e59d300c r3, [sp, #12] 48: e2833001 add r3, r3, #1 4c: e58d300c str r3, [sp, #12] 50: e59d200c ldr r2, [sp, #12] 54: e59d3004 ldr r3, [sp, #4] 58: e1520003 cmp r2, r3 5c: dafffff0 ble 24 <fib+0x24> 60: e59d3010 ldr r3, [sp, #16] ■♥♣✉t ❞❛t❛ t✐♠❡✭ ❍❀ P❀ ❞ ✮ ❞ ∈ D R13 R13 Inst. Data ARM9TDMI Cache Core Cache Coprocessor 15 ❍❛r❞✇❛r❡ ❍ Data Inst. MMU MMU Write Buffer AMBA bus interface ❲❈❊❚✭ ❍❀ P ✮ = ♠❛① ❞ ∈D t✐♠❡✭ ❍❀ P❀ ❞ ✮ ❆❈❙❉✬✷✵✶✶ ✭◆❡✇❝❛st❧❡✱ ❯❑✱ ❏✉♥❡ ✷✵✶✶✮ ❚✐♠❡❞ ●❛♠❡s ❢♦r ❈♦♠♣✉t✐♥❣ ❲❈❊❚ ✶ ✴ ✷✷

❲♦rst✲❈❛s❡ ❊①❡❝✉t✐♦♥✲❚✐♠❡ 10: e3a03000 mov r3, #0 14: e58d3014 str r3, [sp, #20] 18: e3a03002 mov r3, #2 1c: e58d300c str r3, [sp, #12] 20: ea00000a b 50 <fib+0x50> 24: e59d3010 ldr r3, [sp, #16] 28: e58d3018 str r3, [sp, #24] 2c: e59d2010 ldr r2, [sp, #16] 30: e59d3014 ldr r3, [sp, #20] Pr♦❣r❛♠ P add 34: e0823003 r3, r2, r3 38: e58d3010 str r3, [sp, #16] ldr 3c: e59d3018 r3, [sp, #24] 40: e58d3014 str r3, [sp, #20] ldr 44: e59d300c r3, [sp, #12] 48: e2833001 add r3, r3, #1 4c: e58d300c str r3, [sp, #12] 50: e59d200c ldr r2, [sp, #12] 54: e59d3004 ldr r3, [sp, #4] 58: e1520003 cmp r2, r3 5c: dafffff0 ble 24 <fib+0x24> 60: e59d3010 ldr r3, [sp, #16] ■♥♣✉t ❞❛t❛ t✐♠❡✭ ❍❀ P❀ ❞ ✮ ❞ ∈ D R13 R13 Inst. Data ARM9TDMI Cache Core Cache Coprocessor 15 ❍❛r❞✇❛r❡ ❍ Data Inst. MMU MMU Write Buffer AMBA bus interface ❲❈❊❚✭ ❍❀ P ✮ ✔ ❲❈❊❚✲❯❇✭ ❍❀ P ✮ ✔ ✭✶ ✰ ✧ ✮ ✂ ❲❈❊❚✭ ❍❀ P ✮ ❆❈❙❉✬✷✵✶✶ ✭◆❡✇❝❛st❧❡✱ ❯❑✱ ❏✉♥❡ ✷✵✶✶✮ ❚✐♠❡❞ ●❛♠❡s ❢♦r ❈♦♠♣✉t✐♥❣ ❲❈❊❚ ✶ ✴ ✷✷

❘❡❧❛t❡❞ ❲♦r❦ ✫ ❊①✐st✐♥❣ ▼❡t❤♦❞s P❛rt✐❛❧ ➊ ❚❡sts✴❙✐♠✉❧❛t✐♦♥ r❛♥❞♦♠ ❡❛s② t♦ ✐♠♣❧❡♠❡♥t ♣r♦❜❛❜✐❧✐st✐❝ ♥♦t ❡①❤❛✉st✐✈❡ r❡❛❧ ❜♦❛r❞✱ s✐♠✉❧❛t♦r ♥♦t s❛❢❡✿ ❣✐✈❡s ❛ ❧♦✇❡r ❜♦✉♥❞ ❚♦♦❧s✿ ❘❛♣✐❚✐♠❡ ✭❜❛s❡❞ ♦♥ ♣❲❈❊❚✮ ❛♥❞ ▼t✐♠❡ ❊①❤❛✉st✐✈❡ ➊ ❙t❛t✐❝ ❆♥❛❧②s✐s ✫ ■♥t❡❣❡r ▲✐♥❡❛r Pr♦❣r❛♠♠✐♥❣ ✶ ❈♦♠♣✉t❡ ❛ ❝♦♥tr♦❧ ✄♦✇ ❣r❛♣❤ ♦❢ P ❤❛r❞❡r t♦ ✐♠♣❧❡♠❡♥t ✷ ❉❡t❡r♠✐♥❡ ❧♦♦♣ ✉♣♣❡r ❜♦✉♥❞s s❛❢❡✿ ❣✐✈❡s ❛♥ ✉♣♣❡r ❜♦✉♥❞ ✸ ❇✉✐❧❞ ❛ ✇❡✐❣❤t❡❞ ❈❋● ♠❛♥✉❛❧ ❛♥♥♦t❛t✐♦♥s ✹ ❙♦❧✈❡ ❛♥ ✐♥t❡❣❡r ❧✐♥❡❛r ♣r♦❣r❛♠ ❛❧❣♦r✐t❤♠ ✐s ♠♦♥♦❧✐t❤✐❝ ❚♦♦❧s✿ ❇♦✉♥❞✲❚✱ ❖❚❆❲❆✱ ❚✉❇♦✉♥❞✱ ❈❤r♦♥♦s✱ ❙❲❊❊❚ ❛♥❞ ❛✐❚ ✭❆❜s■♥t✮ ❆❈❙❉✬✷✵✶✶ ✭◆❡✇❝❛st❧❡✱ ❯❑✱ ❏✉♥❡ ✷✵✶✶✮ ❚✐♠❡❞ ●❛♠❡s ❢♦r ❈♦♠♣✉t✐♥❣ ❲❈❊❚ ✷ ✴ ✷✷

❘❡❧❛t❡❞ ❲♦r❦ ✫ ❊①✐st✐♥❣ ▼❡t❤♦❞s P❛rt✐❛❧ ➊ ❚❡sts✴❙✐♠✉❧❛t✐♦♥ r❛♥❞♦♠ ❡❛s② t♦ ✐♠♣❧❡♠❡♥t ♣r♦❜❛❜✐❧✐st✐❝ ♥♦t ❡①❤❛✉st✐✈❡ r❡❛❧ ❜♦❛r❞✱ s✐♠✉❧❛t♦r ♥♦t s❛❢❡✿ ❣✐✈❡s ❛ ❧♦✇❡r ❜♦✉♥❞ ❚♦♦❧s✿ ❘❛♣✐❚✐♠❡ ✭❜❛s❡❞ ♦♥ ♣❲❈❊❚✮ ❛♥❞ ▼t✐♠❡ ❊①❤❛✉st✐✈❡ ➊ ❙t❛t✐❝ ❆♥❛❧②s✐s ✫ ■♥t❡❣❡r ▲✐♥❡❛r Pr♦❣r❛♠♠✐♥❣ ✶ ❈♦♠♣✉t❡ ❛ ❝♦♥tr♦❧ ✄♦✇ ❣r❛♣❤ ♦❢ P ❤❛r❞❡r t♦ ✐♠♣❧❡♠❡♥t ✷ ❉❡t❡r♠✐♥❡ ❧♦♦♣ ✉♣♣❡r ❜♦✉♥❞s s❛❢❡✿ ❣✐✈❡s ❛♥ ✉♣♣❡r ❜♦✉♥❞ ✸ ❇✉✐❧❞ ❛ ✇❡✐❣❤t❡❞ ❈❋● ♠❛♥✉❛❧ ❛♥♥♦t❛t✐♦♥s ✹ ❙♦❧✈❡ ❛♥ ✐♥t❡❣❡r ❧✐♥❡❛r ♣r♦❣r❛♠ ❛❧❣♦r✐t❤♠ ✐s ♠♦♥♦❧✐t❤✐❝ ❚♦♦❧s✿ ❇♦✉♥❞✲❚✱ ❖❚❆❲❆✱ ❚✉❇♦✉♥❞✱ ❈❤r♦♥♦s✱ ❙❲❊❊❚ ❛♥❞ ❛✐❚ ✭❆❜s■♥t✮ ❆❈❙❉✬✷✵✶✶ ✭◆❡✇❝❛st❧❡✱ ❯❑✱ ❏✉♥❡ ✷✵✶✶✮ ❚✐♠❡❞ ●❛♠❡s ❢♦r ❈♦♠♣✉t✐♥❣ ❲❈❊❚ ✷ ✴ ✷✷

❖✉r ❈♦♥tr✐❜✉t✐♦♥ ❆ss✉♠♣t✐♦♥s ♦♥ ❜✐♥❛r② ♣r♦❣r❛♠ P ✿ t❡r♠✐♥❛t✐♦♥ ♦❢ P ❞♦❡s ♥♦t ❞❡♣❡♥❞ ♦♥ ✐♥♣✉t ❞❛t❛ P ❛❧✇❛②s t❡r♠✐♥❛t❡s ❘❡s✉❧ts ❋✉❧❧② ❛✉t♦♠❛t✐❝ ❝♦♠♣✉t❛t✐♦♥ ♦❢ ❲❈❊❚ ❝♦♠♣✉t❛t✐♦♥ ♦❢ ❈❋● ✭❛♥❞ st❛❝❦ s✐③❡✮ ❝♦♠♣✉t❛t✐♦♥ ♦❢ ❲❈❊❚✲❡q✉✐✈❛❧❡♥t ♣r♦❣r❛♠ ▼♦❞✉❧❛r ♠❡t❤♦❞ Pr♦❣r❛♠ ♠♦❞❡❧ ✶ ✷ ❍❛r❞✇❛r❡ ♠♦❞❡❧ ✸ ❆♥❛❧②s✐s ✭❝♦♠♣✉t❛t✐♦♥ ♦❢ ❲❈❊❚✮ ❈♦♠♣❛r✐s♦♥ ♦❢ ❝♦♠♣✉t❡❞ ❲❈❊❚ ❛♥❞ ❛❝t✉❛❧ ❲❈❊❚ ❲❈❊❚ ❇❡♥❝❤♠❛r❦s ❢r♦♠ ▼ä❧❛r❞❛❧❡♥ ❯♥✐✈❡rs✐t② ♠❡❛s✉r❡♠❡♥ts ♦♥ r❡❛❧ ♣❧❛t❢♦r♠ ❆❘▼✾✷✵❚ ❲❈❊❚ ❝♦♠♣✉t❡❞ ✇✐t❤ ❯PP❆❆▲ ❬❇❡❝✶✶❪ ❏✳✲▲✳ ❇é❝❤❡♥♥❡❝ ❛♥❞ ❋✳ ❈❛ss❡③✱ ❈♦♠♣✉t❛t✐♦♥ ♦❢ ❲❈❊❚ ✉s✐♥❣ Pr♦❣r❛♠ ❙❧✐❝✐♥❣ ❛♥❞ ❘❡❛❧✲❚✐♠❡ ▼♦❞❡❧✲❈❤❡❝❦✐♥❣✱ ❘❡s❡❛r❝❤ r❡♣♦rt✱ ■❘❈❈②◆✴❈◆❘❙✱ ▼❛② ✷✵✶✶✱ ❛r❳✐✈✿✶✶✵✺✳✶✻✸✸✈✷ ❬❝s✳❙❊❪✳ ❆❈❙❉✬✷✵✶✶ ✭◆❡✇❝❛st❧❡✱ ❯❑✱ ❏✉♥❡ ✷✵✶✶✮ ❚✐♠❡❞ ●❛♠❡s ❢♦r ❈♦♠♣✉t✐♥❣ ❲❈❊❚ ✸ ✴ ✷✷