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Reconfigurable Computing Reconfigurable Computing VHDL Crash Course VHDL Crash Course Chapter 2 Chapter 2

• Prof. Dr.
• Prof. Dr.-
• Ing. J
• Ing. Jü

ürgen Teich rgen Teich Lehrstuhl f Lehrstuhl fü ür Hardware r Hardware-

• Software

Software-

• Co

Co-

• Design

Design

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VHDL VHDL

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VHDL: Very high speed integrated circuits Hardware Description Language

• Hardware description for

– patent application – simulation – synthesis of ICs

• Description covers the aspects of

– wiring – behaviour structure – hierarchy

• Here: only synthesizable subset !

Entity Entity – – Wrapper and interface definition Wrapper and interface definition

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• Logical container of an entity
• Port definition of the interface: signals

X

• Signals are defined by an identifier, a

direction and a data type

– direction: in, out, inout, buffer – data types: bit, std_logic(_vector), ADT

ENTITY

x x

Parameter

x

ENTITY

x2 y x1

ENTITY

x2 y x1

External signals correspong to internal signals. External view Internal view

Entity as a Entity as a „ „Black Box Black Box“ “

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• Entity as a „black box“

seperation of internal structur and behaviour (functionality)

• Example: Entity with 2 input and 1 output
• Ports are defined but functionallity yet undefined.

two_gate

Name Port

x1 x2 Structure and behaviour? y

Port

Entity Entity – – Example Example

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5 Keywords in blue

LIBRARY ieee; USE ieee.std_logic_1164.all;

Used libraries Which packages of the library are to be used

Header

Name of the Entity Interface 2 input signal named x1 and x2 data types of the signals (multivalued logic) Name of the Entity

Entity definition

• utput signal

named y

ENTITY two_gate IS PORT ( x1, x2 : IN std_logic; y : OUT std_logic ); END two_gate;

Keywords are spelled either in upper or lower case but never mixed!

Architecture Architecture – – Behaviour of an Entity Behaviour of an Entity

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• The functionallity of an entity is

described in its architecture.

• The architektur

– has a unique name, – may contain a declaration part for internal signals, – is assigned to an entity.

• It is possible to define different architectures for the

same Entity.

x1 x2 y Structure and behaviour Architecture ARCHITECTURE <architecturename> OF <entityname> IS [declaration part] BEGIN [architecture statements] END <architecturename>;

Architecture Architecture – – Example Example

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&

x1 y x2

Architecture

• Example of a NAND gate

based on the previous entity declaration:

ARCHITECTURE two_gate_nand OF two_gate IS BEGIN y <= NOT ( x1 AND x2 ); END two_gate_nand;

Behavioural description: One statement using the predefined

• perations: AND, OR,

NOT Architecture name Assignment

• perator

for signals Architecture name Entity Name

Configuration Configuration – – the link the link

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The configuration assigns a behaviourial description to it's entity.

– Different behaviourial descriptions for simulation and synthesis. different aspects of the functionality simulation complexity and performance – Interface definition is valid for a class of entities, e.g.: AND, OR, XOR-gates with 2 inputs each

• nly a new behavioural desciption needs to be created

Configuration Configuration – – Example Example

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• The configuration assigns an architecture to the entity.

two_gate_nand_conf

x1 x2 y

&

x1 y x2

VHDL comments started by: -- Entity name

• - Configuration for nand with two Inputs

CONFIGURATION two_gate_nand_conf OF two_gate IS FOR two_gate_nand . . . END FOR; END two_gate_nand_conf;

Name of the architecture to use Configuration name

Progress Progress

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• Covered so far:

– Entity wrapper and interface definition of the logical unit – Architecture describes the behaviour or structure of the entity – Configuration links one architecture to an entity

• Still missing:

– Components

• to create structural descriptions
• to introduce hierarchy

– Processes – Control flow, state machines and bit vectors – timing models – simulation using testbenches

Use of components Use of components

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• Hierarchical use of components
• Complex gates - example: XOR

– structural description – ports: 2 inputs and 1 output – reuse of two_gate, with the new name xor_gate.

& &

≥

x1 y Possible structure of the entity xor_gate: Components

• ent1, ent2 (and gates)
• ent3 (or gates)
• inv1, inv2 (inverter)

x2

xor

ent1 x1 x1 x1 x2 x2 y y y y ent2 ent3 x1 x2

connect2 connect1 inv1 inv2

x2

≥ & &

¬ ¬

XOR XOR-

• Entity

Entity

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• Entity declaration

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY xor_gate IS PORT( x1, x2 : IN std_logic; y : OUT std_logic ); END xor_gate;

XOR XOR – – Declarations Declarations

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• Architecture declaration
• Instantiation of components

ARCHITECTURE xor_structure OF xor_gate IS COMPONENT two_gate PORT ( x1, x2: in std_logic; y: out std_logic ); END COMPONENT; SIGNAL connect1, connect2: std_logic; SIGNAL inv1, inv2: std_logic; BEGIN ... Declaration of a gate with 2 inputs and 1 output 2 signals for the and and

• r gates

2 signals to connect the inverted input signals

XOR XOR – – Instantiation Instantiation

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• Instantiation and connection of the components

... ent1: two_gate PORT MAP (x1 => x1, x2 => inv1, y => connect1 ); ent2: two_gate PORT MAP (x1 => inv2, x2 => x2, y => connect2 ); ent3: two_gate PORT MAP (x1 => connect1, x2 => connect2, y => y );

...

instanc e name type of entity Connection: intern => extern (from the point of view of the component)

xor

ent1 x1 x1 x1 x2 x2 y y y y ent2 ent3 x1 x2

connect2 connect1 inv1 inv2

x2

≥ & &

¬ ¬

XOR XOR – – Connections in detail Connections in detail

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ent1 x1 x1 x2 y

connect1 inv1

&

ent1: two_gate PORT MAP ( x1 => x1, x2 => inv1, y => connect1 );

x1 x2 y ent2

connect2 inv2

x2 &

ent2: two_gate PORT MAP ( x1 => inv2, x2 => x2, y => connect2 );

y y ent3 x1 x2

connect2 connect1

≥

ent3: two_gate PORT MAP ( x1 => connect1, x2 => connect2, y => y );

Process evaluation cycle Process evaluation cycle

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• Evaluation of a process:

– Instruction inside a process are evaluated sequentially! – A process can be considered to be an infinite loop – A process requires at least one time consuming statement (change of signal, time, event) to prevent cycles with no time requirements

process evaluate sequentially triggered event triggered signals stable

Evaluate signal assignments and forward to end of process Variables are assigned and evaluated immediatly

Syntax of a process Syntax of a process

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... BEGIN [label:] PROCESS ( x1, x2, ... ) BEGIN Prozessrumpf; END PROCESS [label]; END;

Process name (optional) Inside an architecture Sensitiviy list: Signal changes evoke process avaluation. Analogous to: „wait for changes

• f x1 or x2“

(alternative: process intern wait-statements) Attention: Signal assignments (<=) differ from signal assignment in programming languages! VHDL A <= B; C <= A; JAVA A = B; C = A;

=

Process name (optional)

Syntax of a process Syntax of a process

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Signal a, b : bit; ... PROCESS ( a ) Variable v : bit; BEGIN a <= NOT b; v := NOT a; b <= a OR v; a <= b; END PROCESS; aini start of process vini bini Signal a Variable v end of process _ bini _ aini

_ aini or aini

bini

Overwrites value!

_ aini

immediatly

Signal b

Sequential evaluation. Called until all triggered signals become stable at the end of the process.

≡ WAIT ON a ;

XOR XOR-

• Architecture

Architecture

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• Negation of input signals

...

INV : PROCESS ( x1, x2 ) BEGIN inv1 <= NOT x2; inv2 <= NOT x1; END PROCESS INV; END xor_arch;

Process name Sensitivity list Assignment of negated input signal

xor

x1 x2

inv1 inv2

¬ ¬

XOR XOR-

• Configuration

Configuration

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• Assignment of behavioural descritption to the instantiated

entity

CONFIGURATION xor_conf OF xor_gate IS FOR xor_behavior FOR ent1,ent2 : two_gate USE ENTITY work.two_gate(two_gate_and); END FOR; FOR ent3 : two_gate USE ENTITY work.two_gate(two_gate_or); END FOR; END FOR; END xor_conf;

Entity 1 und 2 are of type: two_gate Use the following entity Entity name Assigned architecture

• f the entities: AND-

gate Assigned architecture

• f the entity: OR-gate

Control Flow Control Flow

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• Branches

– IF – THEN – ELSE – CASE ( y of type std_logic: 1, 0, Z, X, … ) LOGIC : PROCESS ( x1, x2, x3 ) BEGIN IF ( x1 = '1' ) THEN y <= '0' ; ELSIF ( x2 = '1' ) THEN y <= '1' ; ELSE y <= 'Z' ; END IF; ...

...

CASE x3 IS WHEN '0' => z <= '0' ; … WHEN others => z <= '1' ; END CASE; END PROCESS LOGIC;

Default case Not elseif!

State Machines State Machines

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• State based Moore- oder Mealy automata
• State transition: current_state next_state

Definition of a state vector

TYPE state_type IS ( S0, S1 ) ; SIGNAL current_state, next_state: state_type ; Automata : PROCESS ( current_state ) BEGIN CASE current_state IS WHEN S0 => next_state <= S1 ; ... WHEN others => next_state <= S0 ; ... END CASE; END PROCESS Automata;

Instantiation of a state vector Assignment of state transition In this case assignment of

• utput as well !!

default case

S0 S1 ? ?

State Machines State Machines

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• Actual state transition in seperate process
• Asynchrounos reset reset to state „S0“
• Synchrounes state transition on rising edge of clock

signal „CLK“ ...

Synch : PROCESS ( CLK, RESET ) BEGIN IF ( RESET = '1' ) THEN

• - define an asynchronous reset

CURRENT_STATE <= S0; ELSIF ( CLK'EVENT and CLK = '1' ) THEN CURRENT_STATE <= NEXT_STATE; END IF; END PROCESS Synch;

Triggered on rising CLK-edge State transition

S0 S1

CLK CLK

Bitvectors Bitvectors

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• Individual signals can be combined to vectors:

std_logic std_logic_vector( )

• Example: position coded with 3 bits

ENTITY Position IS PORT( SOLL : in std_logic_vector( 2 downto 0 ); IST : out std_logic_vector( 0 to 2 ) ); END Position; 3 bit wide binary coded bit vector. Use of (x downto y) corresponds to the usual interpretation of the binary digits in terms of MSB and LSB (MSB: most significant bit, LSB: least ...)

22 1 1 0 21 20 LSB MSB value: 6 20 1 1 0 21 22 MSB LSB value: 3

Rising significance Rising significance

Simulation Simulation – – Testbenches Testbenches

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• Testbench

– Entity without external ports – Instantiates the unit under test (UUT) as a component – Generates test data (test stimuli) – The generate test stimuli are applied to the UUT as inputs

• Simulation Functional Test

– Observation of outputs and internal states of the UUT.

• Testbenches are programmed the same way as any
• ther entity.

Application of the learned methods for „regular“ entities.

Testbench Testbench-

• Entity

Entity

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• Empty wrapper to instantiate the entity under test.

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY my_tb IS END my_tb ;

Testbench name

my_tb

No port definition

Testbench Testbench-

• Architecture

Architecture

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• Declaration of the unit under test
• Local signals to connect the UUT
• Declaration of signals and components ant the beginning of the

architecture.

ARCHITECTURE my_tb_behavior OF my_tb IS SIGNAL tb_x1, tb_x2, tb_y : std_logic; COMPONENT xor_gate PORT( x1, x2 : in std_logic; y: out std_logic ); END COMPONENT; BEGIN ... Testbench Name Testbench architecture name 3 local signals Declaration of the UUT Type of component Interface definition

Testbench Testbench-

• Architektur

Architektur

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• Instantiation and connection of the component

... BEGIN test_ent : xor_gate PORT MAP (x1 => tb_x1, x2 => tb_x2, y => tb_y ); ... Instantiation of a component with a name

my_tb tb_x1 tb_x2 tb_y x1 y x2

test_ent Component type Component port Local signal Connection: component port => local signal

Testbench Testbench-

• Architecture

Architecture

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• Generate test patterns (stimuli) in a process
• time statements can not be synthesized, but testbenches are

never synthezised anyway!

Process name ... my_stimuli : PROCESS BEGIN tb_x1 <= '0'; tb_x2 <= '0'; WAIT FOR 10 ns ; tb_x1 <= '1'; WAIT FOR 10 ns ; tb_x1 <= '0' AFTER 5 ns ; .... END PROCESS my_stimuli; Assign this value for a period of 10 ns. Time passes! Assignment of values to signals Only tb_x1 is assigned a new value, tx_x2 remains unchanged Assign this value after 5 ns. Add to signal-schedule-list

Timing Timing-

• Description

Description

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• Timing can be modeled in several ways

– wait for – after – Sensitivliste

• Use of generic parameters

– In this case: delayed assignment (delay of output: del_time: time) ENTITY two_gate IS GENERIC( del_time: time := 2 ns ); PORT( x1, x2: in std_logic; y: out std_logic ); END two_gate; ARCHITECTURE two_gate_del_nand OF two_gate IS BEGIN y <= NOT ( x1 AND x2 ) AFTER del_time; END two_gate_del_nand ; Delayed assignment after 2ns Parameter für delaytime with default value

Simulation Simulation – – vhdldbx vhdldbx

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• vhdldbx as Simulator (Synopsys)

– Selection of entity to test – Hierarchy Browser – Wave-Form-Viewer

• Alternative: Modelsim (Mentor Graphics)
• Stimuli from testbench (Test-Input)
• Simulation result is the signal trace, showing the

effect of the stimuli on the tested signals.

Simulation Simulation – – Hierarchy Browser Hierarchy Browser

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• Hierarchy Browser to select the signals to simulate

Example for selection of signals. In this case XOR!

XOR XOR-

• Simulation

Simulation

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• Simulation using vhdldbx in the Wave-Form-Viewer