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Real-Time Resampling Processor for SWARM Mark Peryer Harvard - - PowerPoint PPT Presentation
Real-Time Resampling Processor for SWARM Mark Peryer Harvard - - PowerPoint PPT Presentation
Real-Time Resampling Processor for SWARM Mark Peryer Harvard Smithsonian Center for Astrophysics August 16, 2017 Presentation Overview Background Objectives Design Results Future work Background Event Horizon Telescope (EHT) Image the
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Background
Event Horizon Telescope (EHT)
Image the event horizon of SgrA* Global network of telescopes Very Long Baseline Interferometry (VLBI)
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Submillimeter Array
Mauna Kea, Hawaii 8 element interferometer 32 GHz instantaneous bandwidth
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SWARM
ROACH2 platform ADCs record data at 4.576 GSps One Quadrant = ~38 Gigabits every second!
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Compatibility Issue SMA
4.576 GHz Frequency Domain ≠
EHT
4.096 GHz Time Domain
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APHIDS
Non-real-time GPU resampling system
ROACH2 ROACH2 ROACH2 ROACH2 ROACH2 ROACH2 ROACH2 ROACH2
SWITCH
10 GbE
SWARM
Single Quadrant
SDBE
ROACH2
UDP VDIF Time q2 UDP VDIF Time q2 UDP VDIF Time q2 UDP VDIF Time q2 4.69 Gbps 4.69 Gbps 9.38 Gbps 4.75 Gbps
Aggregate Data Rates 37.50 Gbps Into Switch/SDBE 18.99 Gbps Into Mark 6
Mark 6
Data Recorder
GPU Server
q2 VDIF unpack 16K-pt FFT N-pt FFT M-pt FFT q2 VDIF unpack 16K-pt FFT N-pt FFT M-pt FFT q2 VDIF unpack 16K-pt FFT N-pt FFT M-pt FFT q2 VDIF unpack 16K-pt FFT N-pt FFT M-pt FFT TCP VDIF TCP
GeForce GTX 980 GeForce GTX 980 GeForce GTX 980 GeForce GTX 980
Mark 6
Data Recorder
Mark 6
Data Recorder Disk transport post-observation
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Improvements
APHIDS
𝙔 Costly 𝙔 Time Inefficient 𝙔 Quantization Error
Real-Time Resampler
✓Inexpensive ✓ Instantaneous Results ✓ Limited Quantization Error
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Target Hardware
SKARAB
Virtex 7 FPGA 40 GbE interface
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40GbE (Rx) Depacketize (B-engine) Data Transpose Data Reprocessing Packetize (VDIF) 40GbE (Rx) 32768 point Inverse FFT Resampling Requantize
High-Level Overview
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Resampling
4576 4096 = 143 128 Upsample by 128 Downsample by 143
⬇ 2
L LPF H(k)
M
Input
⬆ 3
LPF
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Practicality
⬆128 ⬇143 585 billion samples every second! Throw away 581 billion samples
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Solution
⬆16 ⬇17.875
128 143 16 8 13 11 4576 4096 = 16 143/8 = 16 17.875
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z-1 z-1 b0 b1 b2 b3 ∑ ∑ t0 t1 t2 3b0 +2b2 4b0 +3b2 5b0 +4b2 t0 t1 t2 2b1 +1b3 3b1 +2b3 4b1 +3b3
z-1 z-1 z-1 b0 b1 b2 b3 ∑
Upsampling
F 2F F F
Inefficient Clock rate increased Efficient Clock rate unchanged
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4 samples every clock cycle 1 new sample every 16 clocks Pattern repeats for parallel inputs
Scaling Up
Time
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FIR Filter
63rd order FIR filter Low pass filter 64 coefficients Least-squares linear phase
Magnitude response of filter
Fpass = 2.138 GHz Fstop = 2.288 GHz
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16 Filters 1024 multiplies 768 adds
FIR Filter Design
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Downsampling
16 outputs every clock ⬇ by 17 and 18 ROM stores mux select Repeats every 143 clocks
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Simulated Input
1 GHz sine wave 4.576 GHz sample rate 16 parallel samples per clock
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Simulated Results
Theoretical output from MATLAB Output from Simulink Design
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Bit Growth
16_14 bit input 16_14 bit coefficients 34_28 bit output 8_7 bit input 8_7 bit coefficients 18_14 bit output Full bit depth Reduced bit depth
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Resource usage
LUTs 7% Reg. 0.5% BRAMs 0.5% DSPs 0%
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Conclusion
Real Time Implementation Parallel FIR Filter Design Fits on Target Hardware
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Future Work
Remove invalid outputs Incorporate into Real-Time Resampling System
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Acknowledgements
Jonathan Weintroub Sheperd Doeleman André Young Rurik Primiani Bob Wilson Arash Roshanineshat SKA Team Casper Community
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