Rapid and Accurate Latch Characterization via Direct Newton - - PowerPoint PPT Presentation
Rapid and Accurate Latch Characterization via Direct Newton Solutions of Setup/Hold Times Shweta Srivastava, Jaijeet Roychowdhury Dept of ECE, University of Minnesota, Twin Cities shwetas@umn.edu 1 Outline Current method for finding setup
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Shweta Srivastava, Jaijeet Roychowdhury
Dept of ECE, University of Minnesota, Twin Cities shwetas@umn.edu
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Current method for finding setup and hold times
Motivation and basic idea Contribution:
Development of fast characterization method.
Problem formulation as a scalar nonlinear algebraic equation. Solving the formulated problem via Newton-Raphson.
Results and conclusion
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D Q
clock
time
Q: output waveforms
setup skew Clock-to-Q delay data data clock
Failed Transition Bad, Not desirable
Clock Edge
time
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Setup Time: Value of setup skew (delay from data
transition edge to clock transition edge) for which clock-to-q delay increases by a certain amount (typically 10%) from the nominal clock-to-q delay.
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Finding setup time via Bisection method
Setup skew: Clock-to-Q delay 10% increase in clock-to-q delay
Setup time Characterization: Bisection method
setup time (not very accurate)
clock
Q
Clock -to-q delay Fixed hold skew
Not to scale
D Q data clock Large number of transient simulation: Expensive
Problem
Nominal Clock-to-Q delay
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Current Characterization Method: Expensive
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Setup and Hold times: prerequisite for timing analysis.
Characterization of standard cell library takes months. Need to reduce the characterization time. without losing accuracy.
Solution
employ Newton-Raphson based solution.
A moderate reduction in computation time (i.e less number of transient simulations) can be significant.
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Formulate the problem of characterization as a scalar
nonlinear algebraic equation A scalar equation with one unknown: setup time Solve the equation via Newton-Raphson method Can hope to converge to solution faster
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Problem Formulation: Finding Setup Time
nominal clock-to-q delay 10% increased clock-to-q delay unknown known quantities
Q output waveform for different setup skews
D Q
clk
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clk clk clk clk clk clk clk clk D Q 1 2 3 4 5 6 7 8
Positive-edge triggered master-slave register
Vector of unknown voltages Q output Unit vector
Selection of Q
clk
D Q
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D Q clk Register equation Q output waveform
This is the condition we are trying to solve.
known quantities unknown
nominal clock-to-q delay 10% increased clock-to-q delay
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Q output waveform
A scalar nonlinear equation with one unknown. Solution of the equation gives optimal value of tau, i.e. setup time. This 'formulated problem' is very similar to the shooting equation.
unknown
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evaluate evaluate
Newton-Raphson
Run transient simulation
Nonlinear Equation
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Differentiate w.r.t
Register equation
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Can be solved using any integration method: BE, TRAP etc.. is obtained.
Differentiate above equation w.r.t
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evaluate
evaluate Scalar equation that needs to be solved. converged? Exit
yes
No update
Start with initial guess
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Results: C2MOS master-slave register
Positive-edge triggered register
4x-6.5x Speedups Initial guess for setup time was accurate up to 1 digit of accuracy.
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Results: Transmisson gate based register
Positive-edge triggered master-slave register
~2.5X Speedups Initial guess of setup time was accurate up to 2 digit of accuracy.
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Formulation of finding setup/hold times problem as an
equation and its solution via Newton-Raphson. Newton-Raphson based method: Speedup: 2.5x-7.5x Can reduce significant amount of time in characterization?
Up to 2 digits of accuracy: Not very useful For 3-7 digits of accuracy: 30 days
11- 3 days Faster design cycle. NR: Good for multivariate unknowns. Months 11- 4 days