= Set Reset 0 S 0 R Q Q Q Q Sequential Logic 3 - PowerPoint PPT Presentation

λ Processor: Data Path Components CS 251 Fall 2019 CS 240 Spring 2020 Principles of Programming Languages Foundations of Computer Systems Ben Wood Ben Wood Sequential Logic 2 1 3 Latch: CC-BY Rberteig@flickr and State Instruction ALU Registers Fetch and Memory Decode Output depends on inputs and stored values . (vs. combinational logic: output depends only on inputs) Elements to store values: latches, flip-flops, registers, memory https://cs.wellesley.edu/~cs240/s20/ Sequential Logic 1 Sequential Logic 2 Bistable latches SR latch S R Q Q' Q (stable) Q' (stable) 0 0 0 1 0 1 0 0 1 0 1 0 Suppose we somehow get a 1 (or a 0?) on here. 1 0 ? ? 1 0 Q Q 0 1 ? ? 0 1 = Set Reset 0 S 0 R Q Q Q Q Sequential Logic 3 Sequential Logic 4

SR latch D latch Q R R D Q Q S Data bit R Q R Q Q C S Q Q S Clock S if C = 0, then SR latch stores current value of Q. S R R Q if C = 1, then D flows to Q: Q Q if D = 0, then R = 1 and S = 0, Q = 0 if D = 1, then R = 0 and S = 1, Q = 1 Q S Sequential Logic 5 Sequential Logic 6 ex Time matters! Clocks Clock: free-running signal with fixed cycle time = clock period = T. D Clock frequency = 1 / clock period C Falling edge Q Rising edge Clock period A clock controls when to update a sequential logic element's state. Assume Q has an initial state of 0 Sequential Logic 7 Sequential Logic 8

Synchronous systems D flip-flop with falling-edge trigger Inputs to state elements must be valid on active clock edge. leader follower E D Q Q L Q F D L D F D latch D latch Q C L Q L C F Q F State State element Combinational logic element 1 2 C Q next becomes Q now Can still read Q now follower stores E as Q Clock leader stores D as E Time Sequential Logic 9 Sequential Logic 10 ex Time matters! Reading and writing in the same cycle D D Q D Flip-Flop Assume Q is initially 0. Clock C Q C E Q Assume Q and E have an initial state of 0 Sequential Logic 11 Sequential Logic 12

*Half a byte! A 1-nybble* register D flip-flop = one bit of storage (a 4-bit hardware storage cell) 0 D Q D Flip-Flop C Q D Q D Q 1 1 D Flip-Flop D Flip-Flop C Q C Q 0 D Q D Flip-Flop C Q 1 D Q D Flip-Flop Write C Q Clock Sequential Logic 13 Sequential Logic 14 Register file Read register number 1 Register 0 Register 1 M Read register Read ports . . . u Read data 1 r selector 1 x (data out) Read register Register n – 2 Read data 1 w r selector 2 Read ports Register n – 1 Why 2? Read data 2 Write register w selector Read register r number 2 Write data w Write? Write port M 0 = read u Read data 2 1 = write r = log 2 number of registers x w = bits in word Array of registers, with register selectors, write/read control, input port for writing data, output ports for reading data. Sequential Logic 15 Sequential Logic 16

Write port (data in) RAM (Random Access Memory) write control clock Write C 0 Register 0 1 D . n -to-2 n . register number Register number . decoder C A B Register 1 n – 2 D n – 1 . . . C Register n – 2 D C Register n – 1 incoming data Register data D Similar to register file, except… Sequential Logic 17 Sequential Logic 18 16 x 4 RAM 4-bit address 1101 4 to 16 decoder data out Sequential Logic 19