= Set Reset 0 S 0 R Q Q Q Q Sequential Logic 3 - - PowerPoint PPT Presentation

CS 251 Fall 2019 Principles of Programming Languages

Ben Wood

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CS 240 Spring 2020

Foundations of Computer Systems

Ben Wood https://cs.wellesley.edu/~cs240/s20/

Sequential Logic and State

Output depends on inputs and stored values. (vs. combinational logic: output depends only on inputs) Elements to store values: latches, flip-flops, registers, memory

Latch: CC-BY Rberteig@flickr

Sequential Logic 1

ALU

Processor: Data Path Components

Registers Memory

Instruction Fetch and Decode

1 2 3

Sequential Logic 2

Bistable latches

Q Q

Suppose we somehow get a 1 (or a 0?) on here.

Q Q

=

Sequential Logic 3

SR latch

Q Q R S Set Reset S R Q Q' Q (stable) Q' (stable) 1 1 1 1 1 ? ? 1 1 ? ? 1

Sequential Logic 4

SR latch

Q Q R S Q Q R S Q Q R S R S Q Q R S Q Q

Sequential Logic 5

D latch

if C = 0, then SR latch stores current value of Q. if C = 1, then D flows to Q: if D = 0, then R = 1 and S = 0, Q = 0 if D = 1, then R = 0 and S = 1, Q = 1

Sequential Logic 6

D C R S Q Q Clock Data bit

Time matters!

D C Q

Assume Q has an initial state of 0

ex

Sequential Logic 7

Clocks

Clock: free-running signal with fixed cycle time = clock period = T. Clock frequency = 1 / clock period A clock controls when to update a sequential logic element's state.

Sequential Logic 8

Clock period Falling edge Rising edge

Synchronous systems

Inputs to state elements must be valid on active clock edge.

Sequential Logic 9

State element 1 State element 2 Combinational logic

D flip-flop with falling-edge trigger

Sequential Logic 10

D C Q E

QL DL CL

D latch

QL QF DF CF

D latch

QF

Q

leader follower

Clock

leader stores D as E follower stores E as Q Can still read Qnow Qnext becomes Qnow

Time

Time matters!

D C E Q

Assume Q and E have an initial state of 0

ex

Sequential Logic 11

Reading and writing in the same cycle

Assume Q is initially 0.

Q D C D Flip-Flop Q Clock

Sequential Logic 12

D flip-flop = one bit of storage

Sequential Logic 13

Q D C D Flip-Flop Q 1

A 1-nybble* register

(a 4-bit hardware storage cell)

Sequential Logic 14

Write Clock

1 1 Q D C D Flip-Flop Q Q D C D Flip-Flop Q Q D C D Flip-Flop Q Q D C D Flip-Flop Q

*Half a byte!

Register file

Read ports Why 2?

Read register selector 1 Read register selector 2 Write register selector Write data Write? Read data 1 Read data 2

r r r w w w

r = log2 number of registers w = bits in word

Array of registers, with register selectors, write/read control, input port for writing data, output ports for reading data. Write port

0 = read 1 = write

Sequential Logic 15

Read ports (data out)

Sequential Logic 16

Read register number 1 Register 0 Register 1 . . . Register n – 2 Register n – 1 M u x Read register number 2 M u x Read data 1 Read data 2

Write 1 n-to-2n decoder n – 2 n – 1 Register 0 C D Register 1 C D Register n – 2 C D Register n – 1 C D . . . Register number . . . Register data

Write port (data in)

Sequential Logic 17

incoming data register number write control clock

RAM (Random Access Memory)

Similar to register file, except… A B

Sequential Logic 18

16 x 4 RAM

19

4 to 16 decoder data

• ut

1101

4-bit address

Sequential Logic