Previous Lecture Slides for Lecture 5 ENCM 501: Principles of - - PDF document

Slides for Lecture 5

ENCM 501: Principles of Computer Architecture Winter 2014 Term Steve Norman, PhD, PEng

Electrical & Computer Engineering Schulich School of Engineering University of Calgary

23 January, 2014

ENCM 501 W14 Slides for Lecture 5

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Previous Lecture

◮ a little more about die yield ◮ measuring and reporting computer performance ◮ quantitative principles of computer design

ENCM 501 W14 Slides for Lecture 5

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Today’s Lecture

◮ ISA design ideas ◮ the ISA view of memory ◮ addressing modes

Related reading in Hennessy & Patterson: Sections A.1–A.3

ENCM 501 W14 Slides for Lecture 5

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ISA versus Microarchitecture

As stated before, here are two important parts of computer architecture:

◮ What instructions are available to applications

programmers? (Usually indirectly, via compilers.) This is

• ften called instruction set architecture, or ISA.

◮ Given the ISA, how exactly are instructions handled by

processors—how deep are pipelines; can instructions be executed out-of-order? How is the memory system organized to minimize loss of clock cycles in fetching instructions and reading and writing data? This category of concern is sometimes called microarchitecture or organization.

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In designing a new microarchitechture for an existing ISA, the goals are

◮ correct machine-language programs must continue to run

correctly;

◮ performance—perhaps running times of tasks, perhaps

energy spent per task, perhaps something else—should be improved. In designing a brand-new ISA or extending an existing ISA in a major way, the concerns are

◮ (one level up, software) making performance wins as

straightforward as possible for compiler writers;

◮ (one level down, microarchitecture) making hardware

implementation reasonable in terms of design and fabrication costs per chip, chip area, energy and power concerns, and so on.

ENCM 501 W14 Slides for Lecture 5

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Classification of ISAs

Section A.2 of the textbook identifies four ISA classes:

◮ stack ◮ accumulator ◮ register-memory ◮ register-register/load-store (which is often shortened to

load-store Stack and accumulator ISAs are now mostly of historical interest, there are important register-memory and load-store architectures in use today.

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Register-memory architectures

In this kind of architecture arithmetic/logical instructions such as ADD, SUB, AND, OR, and SHIFT generally have two

• perands, one of which is allowed to be in memory.

x86 and x86-64 are register-memory ISAs. Example instructions from gcc output for Linux on x86-64 (operands are source first, destination second): mov

• 12(%rbp), %eax

salq $2, %rax addq

• 32(%rbp), %rax

movl (%rax), %eax mov %eax, %eax addq %rax, -8(%rbp) addl $1, -12(%rbp)

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Note that if one operand is in memory, the instruction require a memory read, a memory write, or both. Here an add follows a read: # %rax += Mem[-32 + %rbp] addq

• 32(%rbp), %rax

This needs a read, then an add, then a write: # Mem[-8 + %rbp] += %rax addq %rax, -8(%rbp) Some instructions don’t access data memory at all: addq $4, %rdx # %rdx += 4 addq %rcx, %rax # %rax += %rcx

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Load-store architectures

In this kind of architecture, arithmetic/logical instructions do not access memory. Instead data memory access is isolated within load (memory read) and store (memory write) instructions. Arithmetic/logical instructions typically have three operands. The destination is a register, and sources are either two registers or one register and one immediate value. Here are MIPS64 examples: DADDIU R17, R16, 800 # R17 = R16 + 800 DADDU R18, R18, R8 # R18 = R18 + R8

ENCM 501 W14 Slides for Lecture 5

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RISC versus CISC

CISC: Complex Instruction Set Computer RISC: Reduced Instruction Set Computer The terms RISC and CISC were introduced in the early 1980’s to contrast instruction set design ideas that had dominant up until that time (CISC) with new design ideas (RISC). It’s impossible give a fair portrayal of CISC ideas in one or two slides, but some important design goals in CISC were:

◮ helpfulness to humans writing assembly language code; ◮ helping compiler writers by providing instructions that

were close matches to expressions in higher-level languages.

ENCM 501 W14 Slides for Lecture 5

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Classic CISC architectures

VAX: Produced by Digital Equipment Corporation. For a long time this was the dominant machine in university research

• labs. A lot of important development of the Unix operating

system was done on “VAXen”. Motorola MC68000: A really important series of microprocessor designs. Used in the first Apple Macintosh (1984), and used in Macs until about 1996. Used in the first workstations from Sun Microsystems. Used in a huge number

• f embedded applications.

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A classic CISC instruction

VAX and 68000 were both “memory-memory” architectures. Example 68000 memory-to-memory copy: MOV.W (A0)+, (A1)+ This would read memory using address register A0, write memory using address register A1, and update both registers to point to the next 16-bit word in memory! How many instructions would a similar operation in MIPS64 require?

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RISC design goals

Here are one non-goal and two important goals:

◮ Convenience for humans writing assembly language is not

important.

◮ Supporting efficient microarchitecture, especially pipelined

processing of instructions, is very important.

◮ Making the microarchitecture reasonably simple and clear

is important to writers of optimizing compilers—compilers should be able to schedule instructions efficiently.

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MIPS: A classic RISC architecture

MIPS is one of the earliest RISC architectures, and of the RISC architectures that got serious commercial use, perhaps the “purest” RISC ISA. Notably, almost every MIPS instructions does an update in

• nly one place:

◮ a register—arithmetic/logical instructions, and loads ◮ memory—stores ◮ special update to program counter—branches and jumps

What common MIPS instruction makes two updates?

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The basic CISC versus RISC tradeoff

Suppose a program is compiled for a CISC machine and a RISC machine, assuming similar integrated circuit technology for both processors. CPU time = IC × CPI × clock period The RISC machine code will tend to have a larger IC than the CISC machine code, but if the RISC microarchitecture and compiler are good, the CPI for the RISC machine will be much lower than the CPI of the RISC machine. This turned out to be true for most practical applications, and by 1990 or so, RISC designs dominated the market for “compute-intensive” applications.

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But x86-64 rules in 2014 . . . What happened?

x86 and its successor x86-64 are most definitely CISC ISAs. However . . .

◮ Intel made enormous revenue from sales to PC

manufacturers, and spent it well on R and D.

◮ Moore’s Law has held from its first expression until at

least the present day.

◮ It would have been ridiculous in the 1980’s to dedicate

hardware to translating CISC instructions to RISC “micro-ops” that are relatively easy to pipeline.

◮ By sometime in the 1990’s chip area needed to translate

CISC instructions to RISC micro-ops became small enough to make translation practical. (Of course, putting the story on one slide is oversimplifying things!)

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A surprising benefit of a CISC ISA

IC (instruction count) for a program compiled for CISC tends to be lower than IC for the same program compiled for RISC. (Also, in the specific case of x86, some commonly-used instructions are smaller than the usual 4-byte size of a RISC instruction.) Why does this matter, in an era of very large disk capacity and very large DRAM capacity?

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The rest of the lecture

This will continue under the document camera, and will cover as much of the following as time permits:

◮ the ISA view of data memory—alignment and endianness ◮ the concept of addressing modes

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Upcoming Topics

◮ more about ISA design ◮ basics of caches

Related reading in Hennessy & Patterson: Sections A.4–A.7, B.1–B.2