Prerequisites IC Project and Verification, HT2 IC Project and - - PowerPoint PPT Presentation

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

IC Project and Verification

• Digital -

Introduction

Joachim Rodrigues, Assistant Professor Henrik Sjöland, Professor

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Prerequisites

IC Project and Verification, HT2

Digital VLSI Project

Digital IC Design Computer Architecture

• Intro. to
• Struct. VLSI

Analog IC Design

RISC Processor VLSI Project Analog/ Mixed Signal Project

Digital IC Design

• Intro. to
• Struct. VLSI

Digital IC Design

Recommended

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Grading

• 9 ECTS

– 1 Assignment in UMC 130-nm CMOS – 4 presentations (5 min) – Report

• 3 ECTS

– Verification by Measurement – Report

Total 12 credits, grade 3-5 (dependent on project and performance)

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Scope

A project course to give experience in practical design in a modern design environment. Unique possibility to design an IC! In groups of 2 students

– First half of period 2 will be one assignment to learn the tools – period 3 and 4 will be group projects – verification part

• FPGA: period 4
• ASIC: after the summer

– applications mainly from signal processing

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

“Labs”

• 2 groups are set up for the labs, please sign up on course

homepage.

• We will go through
• the ASIC synthesis flow
• Place and Route (PnR)

Schedule:

• TBD
• Thursday

13:15 – 15:15 The last two lab hours on due date TA’s will only approve the assignments.

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Assignment

In period 2 you need to carry out one assignment which you will take through an entire digital ASIC design flow – Matrix multiplier (controller+datapath)

• RTL implementation
• Simulation
• ASIC Synthesis

– Area/speed constraint

• Physical placement and routing

All tasks need to be completed in time to be able to continue with the project part of the course.

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Matrix Multiplier

• Design Implementation
• A matrix multiplier needs to be implemented in VHDL
• 6x3 matrix, input vector
• Time-multiplexed Architecture is (1 mult, 1add)
• Coefficients are stored in a ROM
• Product needs to be stored in a RAM
• Memories will be provided

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

ASIC Synthesis

• A new synthesis tool will be introduced
• Synopsys design compiler
• Designs needs to be constraint for:
• Mimium area
• Maximum speed
• Netlist simulation
• Design needs to be simulated with timing information

generated during synthesis

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Physical Placement

• A new tool will be introduced
• Cadence SoCEncounter
• Memories and design needs to

be placed and routed:

• Floorplanning
• Power Planning
• Cell/Pad Placement
• Clock tree synthesis
• Signal routing

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Assignment Deadlines

Deadlines MUST be met to be able to continue the course!

• November 3rd: FSMs and datapath
• November 10th: Synthesizable model
• November 17th: ASIC synthesis and netlist simulation
• November 24rd: Physical placement and signal routing

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Plagiasm

Do not copy any material from other students or the internet.

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Project

Beginning of December projects will be conducted in groups of 2 students. Projects will be presented later Examples from previous years

– Pacemaker filter – UMTS filter – FFT/DCT – Color converter – Gaussian filter – Divider using CORDIC – Mixed radix FFT – Media Player

New track: Computer Architecture You will implement a RISC processor on FPGA and you will run a program on it EITF20 is a prerequisite for this track

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Project

2009: 5 projects started – 77 % passed

Initial project presentation include

• project specification
• time‐plan
• expected results

Dec March

• ca. 14 weeks

Final presentation and report 1st presentation

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Grading

Grade will depend on all parts of the course

– assignments – project results – oral presentations – written report

Usually the project/group is given the same grade. However, individual grades might be given depending on the situation, e.g., group dynamics.

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Supervisors

• Assignment

– Nafiseh – Deepak

• Projects

– Johan – Isael – Chenxin – Reza – Deepak – Yasser

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Students’ opinions

• Positiv:

– I got to know the whole process of the digital design follow. – We can design our own chips,which is really exciting and amazing. – Man får se hela utvecklingskjedjan. – This is the most wonderful course I have studied. – En utmärkt kurs som verkligen förbereder ingenjörerna på verkliga problem i arbetslivet. En kurs som sammanfattar alla kunskaper och man får en känsla för hela processen från planering till färdig produkt.

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Students’ opinions

• Negativ:

– Information regarding the fact that verification (and the course) extends over so many quarters. This was not apparent when signing up for the course. – we strongly suggest improving the credits to award the hard−working people a fair feedback. – Lab manual should be more detail. – The credits of this course is only 12 ECTS,I think this number is too low. – We worked 7 months, full day, on it, actually.

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Many students were able to get a Master Thesis at:

• ST-Ericsson (6 students)
• Ericsson (6 students)
• Infineon Austria (1 student)
• ARM (4 students)

Outcome:

• Publications 5: VTC (Taiwan), Globecom (Miami),

Norchip (Scandinavia), Patmos (Delft)

• Patents 2 (Ericsson-STE)
• PhD positions: 2

Life after

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

Questions?

Joachim Rodrigues, EIT, LTH jrs@eit.lth.se

www.lu.se