P4, FPGA, HLS ● Domain-specific language - network data forwarding ■ Standardized and maintained by P4 Language Consortium @ p4.org ■ Independent of network protocols (VLAN, VxLAN, INT, …) and target architectures (ASIC, FPGA, NPU, CPU) ■ Match + Action user-defined packet processing ■ Custom hardware accelerators as externs/instructions ● FPGA as a P4 target ■ ASIC-like performance, deterministic, low-latency processing ■ Higher performance per watt than NPU or CPU ■ Flexibility beyond ASICs (new instructions or externs) ● HLS for P4 to FPGA ■ Unlocks NPU-like programming with ASIC-like performance ■ >10x higher productivity of HLS vs HDL 2
P4 code example Headers Parse graph Tables header_type ethernet_t { #define ETHT_IPV4 0x0800 table tab1 { fields { #define ETHT_IPV6 0x86dd reads { dstAddr : 48; ipv4.identification : exact ; srcAddr : 48; parser start { ipv4.srcAddr : lpm ; etherType : 16; extract (ethernet); ipv4.totalLen : range ; } return select (latest.etherType) { ipv4.dstAddr : lpm ; } ETHT_IPV4 : parse_ipv4; } actions { header ethernet_t ethernet; ETHT_IPV6 : parse_ipv6; route_ipv4; } no_op; header_type ipv4_t { } } fields { max_size : 128; version : 4; parser parse_ipv4 { } ihl : 4; extract (ipv4); diffserv : 8; return ingress; table tab2 { totalLen : 16; } reads { identification : 16; ipv4.dstAddr : lpm ; flags : 3; parser parse_ipv6 { ethernet.srcAddr : range ; fragOffset : 13; extract (ipv6); ipv4.identification : ternary ; ttl : 8; return ingress; } actions { protocol : 8; } drop; hdrChecksum : 16; no_op; srcAddr : 32; } dstAddr : 32; } } } header ipv4_t ipv4; 3
P4 code example Actions Control flow action route_ipv4(dst_mac, src_mac, vid) { control ingress { modify_field (ethernet.dst_addr, dst_mac); apply (tab1); modify_field (ethernet.src_addr, src_mac); apply (tab2) { modify_field (vlan_tag.vid, vid); miss { add_to_field (ipv4.ttl,-1); apply (tab3); } } } action no_op() { if ( valid (vlan_tag[0])) { } apply (port_vlan) { hit { … } } } ... } control egress { ... } 4
P4 pipeline D P E O I A P U N R Queues A T P M+A M+A S Buffers R P U Table Table E S U T R E T R parser match_action deparser 5
Parser in VHDL ● Two configurations: ■ full - Ethernet, 2×VLAN, 2×MPLS, IPv4/IPv6 (with2×extension headers), TCP/UDP, ICMP/ICMPv6 ■ simple L2 - Ethernet, IPv4/IPv6 (with 2×extension headers), TCP/UDP, ICMP/ICMPv6 ● Search of best implementation ■ All possible placements of pipeline among protocol analyzers ■ Two data bus widths 256, 512 ■ O0 - no optimization ■ O1 - offset width ■ O2 - +offset alignment ■ O3 - reworked P4 code ■ O4 - all combined 6
Pareto sets 7
Use Case: 100G In-band Network Telemetry ● Collection and reporting of network state by inserting, analyzing, and stripping INT headers ● P4 to FPGA HLS used to generate firmware for Netcope 100G programmable NIC ● No need to use HDL (hardware description language) ● Ultra-fast time-to-market and wire-speed traffic processing at 100Gbps 8
Thank you for your attention! Lukáš Richter Pavel Benáček Viktor Puš Michal Kekely Try it out at np4.netcope.com!
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