in FPGA HLS to improve Maximum Frequency Licheng Guo*, Jason Lau*, - - PowerPoint PPT Presentation

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in FPGA HLS to improve Maximum Frequency Licheng Guo*, Jason Lau*, - - PowerPoint PPT Presentation

May 27, 2023 131 likes •574 views

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to improve Maximum Frequency Licheng Guo*, Jason Lau*, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang and Jason Cong University of California Los Angeles, Cornell

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SLIDE 1

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to improve Maximum Frequency

Licheng Guo*, Jason Lau*, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang and Jason Cong University of California Los Angeles, Cornell University

* indicates co-first authors https://github.com/Licheng-Guo/vivado-hls-broadcast-optimization

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SLIDE 2

Outline

  • Introduction
  • Problem Classification
  • Solution
  • Experiments
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SLIDE 3

RTL Verilog vs. Untimed C/C++

  • Much higher developing efficiency
  • Less achievable frequency compared to RTL designs
  • Hard to debug the critical path
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SLIDE 4

We Analyze the Timing Issues of Complex Designs

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SLIDE 5

We Analyze the Timing Issues of Complex Designs

  • Most critical paths are related to broadcasts
  • Some are hidden in user codes
  • Some are inferred by the HLS compiler
  • Lead to high-fanout interconnects and bad timing quality
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SLIDE 6

We Analyze the Timing Issues of Complex Designs

  • Most critical paths are related to broadcasts
  • Some are hidden in user codes
  • Some are inferred by the HLS compiler
  • Lead to high-fanout interconnects and bad timing quality
  • We categorize common types of broadcasts in HLS-based designs.
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SLIDE 7

We Analyze the Timing Issues of Complex Designs

  • Most critical paths are related to broadcasts
  • Some are hidden in user codes
  • Some are inferred by the HLS compiler
  • Lead to high-fanout interconnects and bad timing quality
  • We categorize common types of broadcasts in HLS-based designs.
  • We analyze the inherent limitations of current HLS tools exposed by the

broadcast problem

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SLIDE 8

We Analyze the Timing Issues of Complex Designs

  • Most critical paths are related to broadcasts
  • Some are hidden in user codes
  • Some are inferred by the HLS compiler
  • Lead to high-fanout interconnects and bad timing quality
  • We categorize common types of broadcasts in HLS-based designs.
  • We analyze the inherent limitations of current HLS tools exposed by the

broadcast problem

  • Our lightweight solutions bring significant frequency boost on real-world

HLS designs

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SLIDE 9

Outline

  • Introduction
  • Problem Classification
  • Solution
  • Experiments
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SLIDE 10

Classification of Broadcasts

  • Data Broadcast
  • Originate from the source code
  • High fan-out signals in the datapath
  • Can be mapped back to certain lines in the source code
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SLIDE 11

Classification of Broadcasts

  • Data Broadcast
  • Originate from the source code
  • High fan-out signals in the datapath
  • Can be mapped back to certain lines in the source code
  • Control Broadcast
  • Originate from the compiler
  • High fan-out signals from control logic
  • Completely transparent to users
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SLIDE 12

Data Broadcast

  • Scenario 1: unrolled loop
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SLIDE 13

Data Broadcast

  • Scenario 1: unrolled loop
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SLIDE 14

Data Broadcast

  • Scenario 1: unrolled loop
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SLIDE 15

Data Broadcast

  • Scenario 1: unrolled loop

Problem: current HLS delay model does not consider the additional net delay

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SLIDE 16

Data Broadcast

  • Scenario 1: unrolled loop

underestimated delay --> inadequate registering

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SLIDE 17

Data Broadcast

  • Scenario 2: Large buffer
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SLIDE 18

Control Broadcast

  • Scenario 1: Pipeline backpressure
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SLIDE 19

Control Broadcast

  • Scenario 1: Pipeline backpressure
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SLIDE 20

Control Broadcast

  • Scenario 2: Synchronization of parallel logics
  • The compiler infers parallelism from sequential code
  • Insert synchronization logic to guarantee correctness
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SLIDE 21

Control Broadcast

  • Scenario 2: Synchronization of parallel logics
  • The compiler infers parallelism from sequential code
  • Insert synchronization logic to guarantee correctness
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SLIDE 22

Control Broadcast

  • Scenario 2: Synchronization of parallel logics
  • The compiler infers parallelism from sequential code
  • Insert synchronization logic to guarantee correctness

/

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SLIDE 23

Control Broadcast

  • Scenario 2: Synchronization of parallel logics
  • The compiler infers parallelism from sequential code
  • Insert synchronization logic to guarantee correctness

/

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SLIDE 24

Control Broadcast

  • Scenario 2: Synchronization of parallel logics
  • The compiler infers parallelism from sequential code
  • Insert synchronization logic to guarantee correctness

/

reduce-then-broadcast

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SLIDE 25

Summary of Broadcast Types

  • Data Broadcast
  • Loop unrolling: loop-invariants variables will be broadcast
  • Large buffer: logical buffer entity will become scattered memory units
  • Lead to incorrect delay prediction -> bad clock insertion
  • Control Broadcast
  • Pipeline control: backpressure signals are broadcast to the whole datapath
  • Synchronization control: guarantee the correctness of concurrent execution
  • Unscalable broadcast of control signals -> not working for large designs
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SLIDE 26

Outline

  • Introduction
  • Problem Classification
  • Solution
  • Experiments
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SLIDE 27

Broadcast-Aware Scheduling

+ + + + ...

  • Isolate the broadcast skeletons and measure the delay

a broadcast skeleton measure delay

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SLIDE 28

Broadcast-Aware Scheduling

+ + + + ...

  • Isolate the broadcast skeletons and measure the delay
  • The additional delay serve as a conservative calibration

A broadcast skeleton measure delay

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SLIDE 29

Broadcast-Aware Scheduling

  • Example: a genome sequencing accelerator design
  • Broadcast elements to 64 datapaths
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SLIDE 30

Broadcast-Aware Scheduling

  • Example: a genome sequencing accelerator design
  • Broadcast elements to 64 datapaths

0.78 ns

…

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SLIDE 31

Broadcast-Aware Scheduling

  • Example: a genome sequencing accelerator design
  • Broadcast elements to 64 datapaths

…

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SLIDE 32

Broadcast-Aware Scheduling

Delay of the aforementioned path

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SLIDE 33

Broadcast-Aware Scheduling

Delay of the aforementioned path Overrall frequency improvements

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SLIDE 34

Skid-Buffer-Based Pipeline Control

  • Adopt skid buffer for flow control

# item <= 1

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SLIDE 35

Skid-Buffer-Based Pipeline Control

  • Adopt skid buffer for flow control

# item <= 1

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SLIDE 36

Skid-Buffer-Based Pipeline Control

  • Adopt skid buffer for flow control

# item <= 1

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SLIDE 37

Skid-Buffer-Based Pipeline Control

  • Adopt skid buffer for flow control

# item <= 1

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SLIDE 38

Skid-Buffer-Based Pipeline Control

  • Buffer width equals that of the pipeline output
  • Different pipeline stages have different output width

# item <= 1

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SLIDE 39

Skid-Buffer-Based Pipeline Control

  • Buffer width equals that of the pipeline output
  • Different pipeline stages have different output width
  • Dynamic programming to optimize the area overhead

# item <= 1 # item <= 1 # item <= 1

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SLIDE 40
  • Prune away redundant synchronization logic

Synchronization Logic Pruning

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SLIDE 41
  • > 50% improvement on our benchmarks
  • For more details please check our paper :)
  • https://github.com/Licheng-Guo/vivado-hls-broadcast-optimization

Experiment Results

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SLIDE 42
  • We classify and analyze the common types of broadcasts in HLS
  • We propose methods:
  • delay model calibration to optimize the data broadcast
  • min-area skid-buffer to optimize pipeline control
  • synchronization pruning to optimize synchronization broadcast
  • We bring over 50% of frequency gain to well-optimized designs.
  • https://github.com/Licheng-Guo/vivado-hls-broadcast-optimization

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to improve Maximum Frequency

Licheng Guo*, Jason Lau*, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang and Jason Cong University of California Los Angeles, Cornell University