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Overview Recap Declaration of Arithmetic Signals Introduction to Structured VLSI Design Operator Sharing VHDL V Counters Joachim Rodrigues Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

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SLIDE 1

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Introduction to Structured VLSI Design ‐ VHDL V

Joachim Rodrigues

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Overview

  • Recap
  • Declaration of Arithmetic Signals
  • Operator Sharing
  • Counters

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Ram vs Register

RAM characteristics

– RAM cell designed at transistor level – Cell use minimal area – Is combinational and behaves like a latch – For mass storage – Requires a special interface logic

Register characteristics

– DFF (may) require much larger area – Synchronous – For small, fast storage – e.g., register file, fast FIFO

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Register File

Registers are arranged as an 1‐d array

  • Each register is accessible with an address
  • Usually 1 write port (with write enable signal)
  • May have multiple read ports
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SLIDE 2

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Strictly Structured VHDL

  • How is it done?

– Local signals (r, rin) are stored in records and contain all registered values. – All outputs are stored in a entity specific record type declared in a global interface package – enables re‐use. – Use a local variable (v) of the same type as the registered values. – reset handling moves to combinatonial part.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Strictly Structured VHDL‐Advantages

Adding a signal in traditional style

  • Add port in entity declaration
  • Add signal to sensitivity list
  • Add port in component declaration
  • Add port in component instantiation

Adding a signal in Strictly Structured VHDL methodology

  • Add element in record declaration

DUT DUT

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Structured VHDL‐Stored signals

Adding a stored signal in traditional style

  • Add two signals (current, next)
  • Add signal to sensitivity list
  • Add reset value
  • Update on clock edge

Adding a signal in Structured VHDL methodology

  • Add element in declaration record

Comb Next Current Comb rin r

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Reset‐ Synchronous

Advantages

  • Reset presented to all FFs fully

synchronous to the clock and will always meet the reset recovery time.

  • Provides some filtering for the

reset signal such that it is not effected by glitches, unless they

  • ccur right at the clock edge.
  • Recommended for designs where

the reset is generated by a set of internal conditions. The clock will filter the logic equation glitches between clock edges.

Disadvantages

  • Reset signal needs to be long

enough to be captured at active clock edge

  • Logic synthesis cannot easily

distinguish the reset signal from any other data signal. Thus, reset signal may take the fastest path to the FFs by making timing hard to meet.

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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Reset‐ Asynchronous

Advantages

  • High speeds can be achieved, as

the data path is independent of reset signal.

  • The circuit can be reset with or

without a clock present.

  • As in synchronous reset, no work

around is required for logic synthesis.

Disadvantages

  • If the asynchronous reset is

released (reset release or reset removal) at or near the active clock edge of a flip‐flop, the

  • utput of the flip‐flop could go

metastable.

  • Spurious resets can happen due

to reset signal glitches.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL II

Synchronous circuit (Chu 8.2)

  • One of the most difficult design aspects of a sequential

circuit:

– How to satisfy the timing constraints

  • The Big idea: Synchronous methodology

– Group all D‐FFs together with a single clock: – Conceptually you only need to deal with

  • timing constraint of one memory element
  • analyze critical path in CL’s one‐by‐one

– Glitches has no effects as long as the signals are stable before the sampling clock‐edge

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

RT‐Level example

32 48 Y=A*B+C A B C Y

A B C D E

CLK

C

CL

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

RT‐level ex. (FSM/single‐register view)

Y=A*B+C A B C Y

A B C C

CL

D E

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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL II

Any RT‐Level circuit and any FSM can be viewed and described this way:

CL

Inputs Outputs Next state State

REG

RT‐Level

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL II

Writing RT‐level VHDL

  • The technology offers.

– Storage elements: DFF (or latch), w/wo reset etc.) – Combinational circuit building blocks (gates, LUT’s)

  • Write VHDL such that

– synthesis tool can recognize/infer flip‐flops (i.e., use the primitives in the technology, rather than synthesizing these from scratch using gates etc.)

  • Synthesis is then about:

– Recognizing flip‐flops – Synthesizing and optimizing combinatonial logic.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Separation of Comb/Seq

  • The clear separation between sequential and

combinational VHDL assures that only DFF will be connected to the clock signal

  • Criteria for good code quality‐‐maintainability
  • A mixture of combinational and sequential processes is

synthesizable but degrades code quality.

  • Ignored in a lot of VHDL books

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Declaring Arithmetic Signals & Variables

  • NUMERIC_STD offers 2 data types

– SIGNED, UNSIGNED – These are declared in a similar method to ‘std_logic_vector’ – Can be used to ‘declare’ signals, variables, even ports in an entity

  • UNSIGNED

– Assumes that only positive values are going to be used – Example declaration

signal count: unsigned (3 downto 0)

Creates a signal used to store values 0 ‐> 15

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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Basic Arithmetic

SIGNED/UNSIGNED OPERATIONS

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Declaring Arithmetic Signals & Variables

  • SIGNED

– 2’s complement form, with MSB used as a sign bit

– Example declaration signal count: signed (3 downto 0)

Creates a signal used for storing the values ‐8 ‐> +7

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

NUMERIC_STD Package Functions

  • For a detailed list of functions (and their operations) see

the program listing from ‘NUMERIC_STD.VHD’ this is the official IEEE package How to read the package header ?

function “+” (L: UNSIGNED; R: NATURAL) return UNSIGNED

UNSIGNED + NATURAL = UNSIGNED

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

NUMERIC_STD Package Functions

Signed Arithmetic Functions:

i.e. functions to add/ subtract signed numbers

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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

NUMERIC_STD Package Functions

Unsigned Arithmetic Functions:

i.e. functions to add/ subtract unsigned numbers

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

NUMERIC_STD Package Functions

Comparison functions:

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

NUMERIC_STD Package Functions

  • Resize functions

– Used for resizing a signed/ unsigned value – Useful if we want to extract carry bit etc.

  • Example

newvalue = resize(oldvalue, 5)

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Operator sharing

Circuit complexity of VHDL operators varies

  • Arithmetic operators

– Large implementation – Limited optimization by synthesis software

  • Manual optimization may be forced by operator sharing in RTL

– Operator sharing – Functionality sharing

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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Operator sharing cont’d

Multiplexing network are mutually exclusively: – Only one result is routed to output – Selected sig assignment (case statement)

with select_expression select sig_name <= value_expr_1 when choice_1, value_expr_2 when choice_2, value_expr_3 when choice_3, . . . value_expr_n when choice_n;

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example I

Original code:

r <= a+b when boolean_exp else a+c;

Revised code:

src0 <= b when boolean_exp else c; r <= a + src0;

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example II

Original code:

process(a,b,c,d,...) begin if boolean_exp_1 then r <= a+b; elsif boolean_exp_2 then r <= a+c; else r <= d+1; end if end process;

Revised code:

process(a,b,c,d,...) begin if boolean_exp_1 then src0 <= a; src1 <= b; elsif boolean_exp_2 then src0 <= a; src1 <= c; else src0 <= d; src1 <= "00000001"; end if; end process; r <= src0 + src1; Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example Operator Sharing

case when s1 d1 <= a*b; ... when s2 d1 <= b*c; ... when s3 d1 <= a*c; ... end case;

d1←a*b s1 d1←b*c s2 d1←a*c s3

Synthesis tool will infere 3 multipliers Expensive in hardware!

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SLIDE 8

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example Operator Sharing

case when s1 d1 <= a*b; ... when s2 d1 <= b*c; ... when s3 d1 <= a*c; ... end case; case when s1 in1 <= a; in2 <= b; ... when s2 in1 <= b; in2 <= c; ... when s3 in1 <= a; in2 <= c; ... end case; m_out <= in1*in2; How can the number of multipers be reduced?

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Counters

  • Binary
  • Gray counter
  • Ring counter

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Binary Counter

Binary counter:

– State follows binary counting sequence – Use an incrementor for the next‐state logic

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Binary Counter

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SLIDE 9

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Gray Counter

Gray counter:

– State changes one bit at a time – Use a Gray incrementor VHDL is provided in the book

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Ring Counter

Circulate a single 1, e.g., 4‐bit ring counter: 1000, 0100, 0010, 0001

– n patterns for n‐bit register – Output appears as an n‐phase signal

Non self‐correcting design

– Insert “0001” at initialization and circulate the pattern in normal

  • peration

Fastest counter (no combinational logic)

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Ring Counter cont’d

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Deadlines

  • Assignment 2 is due no later than Friday 23th
  • Source code needs to be provided
  • Code must be readable, i.e., use indent etc.

Code Code Code Code Format: Landscape

Bad example Good example

  • next week: Invited Lecture‐Ericsson Research
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SLIDE 10

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Synthesis Summary

Screen dump of the synthesis summary (ALU+FIR) is needs to be handed in with the code.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V