Overview • Recap • Declaration of Arithmetic Signals Introduction to Structured VLSI Design • Operator Sharing ‐ VHDL V • Counters Joachim Rodrigues Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Ram vs Register Register File RAM characteristics Registers are arranged as an 1 ‐ d array – RAM cell designed at transistor level • Each register is accessible with an address – Cell use minimal area • Usually 1 write port (with write enable signal) – Is combinational and behaves like a latch • May have multiple read ports – For mass storage – Requires a special interface logic Register characteristics – DFF (may) require much larger area – Synchronous – For small, fast storage – e.g., register file, fast FIFO Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V
Strictly Structured VHDL Strictly Structured VHDL ‐ Advantages • How is it done? Adding a signal in traditional style • Add port in entity declaration – Local signals (r, rin) are stored in records and contain all • Add signal to sensitivity list DUT registered values. • Add port in component declaration – All outputs are stored in a entity specific record type • Add port in component instantiation declared in a global interface package – enables re ‐ use. – Use a local variable (v) of the same type as the registered values. Adding a signal in Strictly Structured VHDL – reset handling moves to combinatonial part. methodology DUT • Add element in record declaration Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Structured VHDL ‐ Stored signals Reset ‐ Synchronous Adding a stored signal in traditional style Advantages Disadvantages • Add two signals (current, next) Comb • • Reset presented to all FFs fully Reset signal needs to be long • Add signal to sensitivity list synchronous to the clock and will enough to be captured at active • Add reset value always meet the reset recovery clock edge • time. Update on clock edge • Current Next Logic synthesis cannot easily • Provides some filtering for the distinguish the reset signal from reset signal such that it is not any other data signal. Thus, reset Adding a signal in Structured VHDL methodology effected by glitches, unless they signal may take the fastest path • occur right at the clock edge. to the FFs by making timing hard Add element in declaration record to meet. • Recommended for designs where Comb the reset is generated by a set of r rin internal conditions. The clock will filter the logic equation glitches between clock edges. Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V
Reset ‐ Asynchronous Synchronous circuit (Chu 8.2) • One of the most difficult design aspects of a sequential Advantages Disadvantages circuit: • • High speeds can be achieved, as If the asynchronous reset is – How to satisfy the timing constraints the data path is independent of released (reset release or reset reset signal. removal) at or near the active clock edge of a flip ‐ flop, the • The circuit can be reset with or • The Big idea: Synchronous methodology output of the flip ‐ flop could go without a clock present. – Group all D ‐ FFs together with a single clock: metastable. • As in synchronous reset, no work – Conceptually you only need to deal with • Spurious resets can happen due around is required for logic • timing constraint of one memory element to reset signal glitches. synthesis. • analyze critical path in CL’s one ‐ by ‐ one – Glitches has no effects as long as the signals are stable before the sampling clock ‐ edge Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL II RT ‐ Level example RT ‐ level ex. (FSM/single ‐ register view) A 32 A Y A A 48 Y=A*B+C B Y C C CL D Y=A*B+C B C C C B CL C D B E E CLK Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V
RT ‐ Level Writing RT ‐ level VHDL • The technology offers. Any RT ‐ Level circuit and any FSM – Storage elements: DFF (or latch), w/wo reset etc.) can be viewed and described this way: – Combinational circuit building blocks (gates, LUT’s) • Write VHDL such that Inputs Outputs – synthesis tool can recognize/infer flip ‐ flops (i.e., use the primitives in CL the technology, rather than synthesizing these from scratch using gates etc.) • Synthesis is then about: – Recognizing flip ‐ flops REG State Next state – Synthesizing and optimizing combinatonial logic. Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL II Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL II Separation of Comb/Seq Declaring Arithmetic Signals & Variables • The clear separation between sequential and • NUMERIC_STD offers 2 data types combinational VHDL assures that only DFF will be – SIGNED, UNSIGNED – These are declared in a similar method to ‘ std_logic_vector ’ connected to the clock signal – Can be used to ‘declare’ signals, variables, even ports in an entity • Criteria for good code quality ‐‐ maintainability • UNSIGNED – Assumes that only positive values are going to be used • A mixture of combinational and sequential processes is – Example declaration synthesizable but degrades code quality. signal count: unsigned (3 downto 0) Creates a signal used to store values 0 ‐ > 15 • Ignored in a lot of VHDL books Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V
Declaring Arithmetic Signals & Variables • SIGNED – 2’s complement form, with MSB used as a sign bit – Example declaration signal count: signed (3 downto 0) Basic Arithmetic Creates a signal used for storing the values ‐ 8 ‐ > +7 SIGNED/UNSIGNED OPERATIONS Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V NUMERIC_STD Package Functions NUMERIC_STD Package Functions • For a detailed list of functions (and their operations) see Signed Arithmetic Functions: the program listing from ‘ NUMERIC_STD.VHD ’ this is the official IEEE package How to read the package header ? function “+” (L: UNSIGNED; R: NATURAL) return UNSIGNED UNSIGNED + NATURAL = UNSIGNED i.e. functions to add/ subtract signed numbers Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V
NUMERIC_STD Package Functions NUMERIC_STD Package Functions Unsigned Arithmetic Functions: Comparison functions: i.e. functions to add/ subtract unsigned numbers Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Operator sharing NUMERIC_STD Package Functions • Resize functions Circuit complexity of VHDL operators varies – Used for resizing a signed / unsigned value • Arithmetic operators – Useful if we want to extract carry bit etc . – Large implementation – Limited optimization by synthesis software • Manual optimization may be forced by operator sharing in RTL – Operator sharing – Functionality sharing • Example newvalue = resize(oldvalue, 5) Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V
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