Over voltage protection of the Power Supply System for the PXD - PowerPoint PPT Presentation

Over voltage protection of the Power Supply System for the PXD detector. 1. Some definitions - voltage transient and power surge. 2. LT4356-1, LT4356-3 Surge Stoppers from LINEAR TECHNOLOGY 3. Transient Voltage Suppression (TVS) diodes 4. Prototyping PCB 5. Tests and results 6. Plans for 2013 Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 1 INP PAN Krakow

Over voltage and over current can occur because of: - failures of the Power Suppies - lightning - switching transients - inductive kickback – inductive load - shorts and other problems in power wiring What are transients and surges ? Transients as being very fast, but with low total energy < 8.4 ms Surges being slow, prolonged, and with high total energy > 8.4 ms DEPFET we protect from: -failures of the power supply – surges - - transient from fast load varation Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 2 INP PAN Krakow

Principle of suppression: • A blocking device detects excessive current flow, and increases its resistance sharply to hold the load current below some limit. • A shunting device detects excessive voltage, and switches to a low impedance state so that the excess current goes through it, and not through the load. Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 3 INP PAN Krakow

Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 4 INP PAN Krakow

Transient Voltage Suppression Diode Application Notes Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 5 INP PAN Krakow

Sensitive are DHP and DCD chips for over voltage. Negative Voltages Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 6 INP PAN Krakow

Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 7 INP PAN Krakow

OVP test board – 12 channels protected. Two-layers board. Without monitoring and control analog digital steering gate is bypassed Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 8 INP PAN Krakow

Test setup Voltage Regulator Load OVP PCB Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 9 INP PAN Krakow

Simplified layout of one channel sense Voltage Regulator power Front 15 m End 1.8V/2.3A OVP Module Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 10 INP PAN Krakow

Schematic of over voltage protection channel Load TMR Fault Timer Input Differential Amplifier sense Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 11 INP PAN Krakow

„for short transient in duration” Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 12 INP PAN Krakow

„for long transient in duration” Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 13 INP PAN Krakow

Digital control of the Over Voltage Protection board Small, SMD optocouplers are not common. Digital Domain Status bits are sent to the uC, reset (re-enable) bits are sent to the channels. Analog Domain Can the reset (re-enable) signals be common for Xilinx CPLD the single domain ? Gate Domain Should we latch error signal “in the channel” or in the Xilinx (with enable-disable Steering option) ? Domain uC signals Digital optocouplers Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 14 INP PAN Krakow

What next ? 1. to test prototype with PS system – some channels 2. design next prototype which will fit to last version 3. PCB 4. integration with PS System Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 15 INP PAN Krakow

Thank you Dankscheen Xie xie Arigato Danke Dekuji Dziekuje Gracias Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 16 INP PAN Krakow

Backup Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 17 INP PAN Krakow

LTspice Symulation LT1970 Power Op R8 sense- 10 R4 sense+ 10 C3 C4 V6 15 10µ 100n Front End Electronics V10 7 Vcc R17 R3 R1 V+ R23 3k 10k 10k v pos +IN VCsn k 1k R18 VCsrc C8 C9 C10 3k Enable Isrc V8 15 470µ 22µ 100p IRLR2908 Isnk U1 M1 vin IRF7335 V9 OUT M2 R22 R28 R2 Vregu lator Vout+ Filter R19 LT 1970 1k Sense+ 0.1 10m 0.4 R15 ca R24 Sense- R12 C7 3k 0.692 -IN V- 8 R16 10µ Vee R20 3k COM C5 C6 Vout- 0.4 10µ 100n PULSE(1.8 5 5m 1m 1m 5m ) R27 .tran 30m 3.3k V3 15 R21 U4 Vload 3.3k R25 LT 1678 3.3kR26 3.3k Vout R29 R13 10 10k LT4356-3 Surge Stopper Vcc SNS Gate OUT SHDN U2 EN FLT Aout FLT with Fault Latchoff LT 4356-2 FB IN+ FB GND T MR R31 R32 R14 TMR 10k 10k 10k C1 100n V2 R35 5V 3k 3k 10k R33 U5 V7 R38 R34 Vsense 5V LT 1809 R37 3k .param R11=4k R36 *.step param R11 4k 6k 1k {R11} 3k MINUS LT1809 Low Distortion Op Amps Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 18 INP PAN Krakow

input load V(vin) V(vload) V(flt) 5.4V 4.5V 3.6V 2.7V 1.8V 0.9V 0.0V voltage or current fault -0.9V -1.8V -2.7V -3.6V -4.5V 0ms 3ms 6ms 9ms 12ms 15ms 18ms 21ms 24ms 27ms Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 19 INP PAN Krakow

Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 20 INP PAN Krakow

Digital Domain to Front End Electronic from Voltage Regulator DVDD DCD FAULT( 3.5V ) 1.8V/1A UNDERVOLTAGE DHPCORE FAULT ( 1.6V ) 1.2V/580mA UNDERVOLTAGE DHPIO FAULT( 3.5V ) 1.2V UNDERVOLTAGE DVDD SW FAULT 3.3V/24mA UNDERVOLTAGE Digital_Ground DGND Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 21 INP PAN Krakow

Analog Domain from Voltage Regulator to Front End Electronic AVDD DCD FAULT(3.5V) 1.8V/2.3A UNDERVOLTAGE REFIN DCD FAULT 1.1V/360mA UNDERVOLTAGE AmpLow FAULT 0.35V/-1A UNDERVOLTAGE VSOURCE FAULT 0V to 7V/100mA UNDERVOLTAGE Analog_Ground AGND Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 22 INP PAN Krakow

Gate Domain from Voltage Regulator to Front End Electronic GATE ON 1,2,3 FAULT(30 V) -3V to -13V / 60mA UNDERVOLTAGE GATE OFF FAULT(10 V) -3V to +5V / 60mA UNDERVOLTAGE VCCG 1,2,3 FAULT -10V to+1V / 10mA UNDERVOLTAGE Gate_Ground GGND Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 23 INP PAN Krakow

Steering Domain from Voltage Regulator to Front End Electronic CLEAR ON FAULT(30 V) 7V to 25V / 60mA UNDERVOLTAGE CLEAR OFF FAULT(10 V) 0V to 5V / -60mA UNDERVOLTAGE VBULK FAULT 5V to 15V / 10mA UNDERVOLTAGE FAULT VBP (back plane) UNDERVOLTAGE -20V VGUARD FAULT -7V to 0V UNDERVOLTAGE VDRIFT -12V to -5V SUB SUB+3.3V 0.06mA Steering_Ground SGND Bartlomiej Kisielewski, Piotr Kapusta 4-6 February 2013 Wetzlar 24 INP PAN Krakow