Over voltage protection of the Power Supply System for the PXD - - PowerPoint PPT Presentation

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Over voltage protection of the Power Supply System for the PXD - - PowerPoint PPT Presentation

Apr 23, 2023 521 likes •788 views

Over voltage protection of the Power Supply System for the PXD detector. 1. Some definitions - voltage transient and power surge. 2. LT4356-1, LT4356-3 Surge Stoppers from LINEAR TECHNOLOGY 3. Transient Voltage Suppression (TVS) diodes 4.

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SLIDE 1

Over voltage protection of the Power Supply System for the PXD detector.

4-6 February 2013 Wetzlar 1 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

  • 1. Some definitions - voltage transient and power surge.
  • 2. LT4356-1, LT4356-3 Surge Stoppers from LINEAR TECHNOLOGY
  • 3. Transient Voltage Suppression (TVS) diodes
  • 4. Prototyping PCB
  • 5. Tests and results
  • 6. Plans for 2013
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SLIDE 2

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 2

Over voltage and over current can occur because of:

  • failures of the Power Suppies
  • lightning
  • switching transients
  • inductive kickback – inductive load
  • shorts and other problems in power wiring

What are transients and surges ? Transients as being very fast, but with low total energy < 8.4 ms Surges being slow, prolonged, and with high total energy > 8.4 ms DEPFET we protect from:

  • failures of the power supply – surges -
  • transient from fast load varation
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SLIDE 3

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 3

Principle of suppression:

  • A blocking device detects excessive current flow, and increases

its resistance sharply to hold the load current below some limit.

  • A shunting device detects excessive voltage, and switches to a

low impedance state so that the excess current goes through it, and not through the load.

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SLIDE 4

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 4

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SLIDE 5

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 5

Transient Voltage Suppression Diode Application Notes

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SLIDE 6

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 6

Sensitive are DHP and DCD chips for over voltage.

Negative Voltages

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SLIDE 7

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 7

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SLIDE 8

OVP test board – 12 channels protected. Two-layers board. Without monitoring and control

analog

digital steering gate is bypassed

4-6 February 2013 Wetzlar 8 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

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SLIDE 9

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 9

Voltage Regulator OVP PCB Load

Test setup

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SLIDE 10

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 10

Voltage Regulator Front End sense power 15 m Simplified layout of one channel OVP Module 1.8V/2.3A

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SLIDE 11

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 11

Load sense

TMR Fault Timer Input Differential Amplifier

Schematic of over voltage protection channel

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SLIDE 12

4-6 February 2013 Wetzlar 12 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

„for short transient in duration”

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SLIDE 13

4-6 February 2013 Wetzlar 13 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

„for long transient in duration”

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SLIDE 14

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 14

Digital Domain Analog Domain Gate Domain Steering Domain Xilinx CPLD uC signals Digital optocouplers Small, SMD optocouplers are not common. Status bits are sent to the uC, reset (re-enable) bits are sent to the channels. Should we latch error signal “in the channel” or in the Xilinx (with enable-disable

  • ption) ?

Digital control of the Over Voltage Protection board Can the reset (re-enable) signals be common for the single domain ?

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SLIDE 15

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 15

What next ?

  • 1. to test prototype with PS system – some channels
  • 2. design next prototype which will fit to last version
  • 3. PCB
  • 4. integration with PS System
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SLIDE 16

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 16

Thank you Dankscheen Xie xie Arigato Danke Dekuji Dziekuje Gracias

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SLIDE 17

Backup

4-6 February 2013 Wetzlar 17 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

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SLIDE 18

Vee V- OUT Sense+ Filter Sense- Vcc

  • IN

+IN VCsn k VCsrc COM Enable Isrc Isnk V+ U1 LT 1970 M1 IRF7335 V3 15 V6 15 C3 10µ C4 100n C5 10µ C6 100n R15 3k R16 3k V8 15 R17 3k R18 3k R19 1k V10 7 C7 10µ C8 470µ C9 22µ C10 100p R22 0.1 R23 1k R24 0.692 PULSE(1.8 5 5m 1m 1m 5m ) V9 R2 0.4 R20 0.4 U4 LT 1678 R21 3.3k R25 3.3kR26 3.3k R27 3.3k R4 10 R8 10 R12 8 R13 10k R14 10k R28 10m M2 IRLR2908 R29 10 C1 100n R31 10k R32 10k 5V V2 U5 LT 1809 R33 3k R34 3k R35 3k R36 3k R37 {R11} R38 10k V7 5V R1 10k R3 10k T MR FB OUT Gate SNS Vcc SHDN FLT EN GND Aout IN+ U2 LT 4356-2 v pos vin ca Vout+ Vout- Vload sense- sense+ FLT FB MINUS TMR Vout Vsense Vregu lator .tran 30m .param R11=4k *.step param R11 4k 6k 1k

LT1970 Power Op LT1809 Low Distortion Op Amps LT4356-3 Surge Stopper with Fault Latchoff Front End Electronics

4-6 February 2013 Wetzlar 18 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

LTspice Symulation

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SLIDE 19

0ms 3ms 6ms 9ms 12ms 15ms 18ms 21ms 24ms 27ms

  • 4.5V
  • 3.6V
  • 2.7V
  • 1.8V
  • 0.9V

0.0V 0.9V 1.8V 2.7V 3.6V 4.5V 5.4V V(vin) V(vload) V(flt)

input load voltage or current fault

4-6 February 2013 Wetzlar 19 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

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SLIDE 20

4-6 February 2013 Wetzlar 20 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

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SLIDE 21

DVDD DCD 1.8V/1A DHPCORE 1.2V/580mA DHPIO 1.2V DVDD SW 3.3V/24mA from Voltage Regulator to Front End Electronic

FAULT(3.5V) UNDERVOLTAGE FAULT (1.6V) UNDERVOLTAGE FAULT(3.5V) UNDERVOLTAGE FAULT UNDERVOLTAGE

4-6 February 2013 Wetzlar 21 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

Digital Domain

Digital_Ground DGND

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SLIDE 22

AVDD DCD 1.8V/2.3A REFIN DCD 1.1V/360mA AmpLow 0.35V/-1A VSOURCE 0V to 7V/100mA from Voltage Regulator to Front End Electronic

FAULT(3.5V) UNDERVOLTAGE FAULT UNDERVOLTAGE FAULT UNDERVOLTAGE FAULT UNDERVOLTAGE

4-6 February 2013 Wetzlar 22 Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow

Analog Domain

Analog_Ground AGND

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SLIDE 23

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 23

GATE ON 1,2,3

  • 3V to -13V / 60mA

GATE OFF

  • 3V to +5V / 60mA

VCCG 1,2,3

  • 10V to+1V / 10mA

from Voltage Regulator to Front End Electronic

FAULT(30 V) UNDERVOLTAGE FAULT(10 V) UNDERVOLTAGE FAULT UNDERVOLTAGE

Gate Domain

Gate_Ground GGND

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SLIDE 24

4-6 February 2013 Wetzlar Bartlomiej Kisielewski, Piotr Kapusta INP PAN Krakow 24

CLEAR ON 7V to 25V / 60mA CLEAR OFF 0V to 5V / -60mA VBULK 5V to 15V / 10mA VBP (back plane)

  • 20V

from Voltage Regulator to Front End Electronic

FAULT(30 V) UNDERVOLTAGE FAULT(10 V) UNDERVOLTAGE FAULT UNDERVOLTAGE FAULT UNDERVOLTAGE

Steering Domain VGUARD

  • 7V to 0V

FAULT UNDERVOLTAGE Steering_Ground SGND

VDRIFT

  • 12V to -5V

SUB SUB+3.3V 0.06mA