[PPT] - Opportunities and Challenges for Nanoelectronic Devices and PowerPoint Presentation

SLIDE 1

Yoshio Nishi Professor, Electrical Engineering, Material Science and Engineering Director of Research, Center for Integrated Systems Director, Stanford Nanofabrication Facility Stanford University

nishiy@stanford.edu

The Sixth U.S.-Korea Forum on Nanotechnology, April 28-29, 2009, Las Vegas, NV

Opportunities and Challenges for Nanoelectronic Devices and Processes

SLIDE 2

CMOS Scaling is not coming to an end
45 nm is happening
32 nm well on its way
22 nm will happen
Major ongoing transformation of scaling caused by power and

power/density

End of frequency scaling of single core processor
No “10 GHz” microprocessor (with the ~100 W cooling limit)
System performance based on multi-low-power cores and accelerators
Move away from frequency scaling
How many “Moore” generations?
As long as we have affordable lithography

Status Quo for Status Quo for “ “Moore Moore” ” and and “ “More Moore More Moore” ”

G. Shahidi, IBM

SLIDE 3

Paradigm Shift: Hitting the Cooling Limit

Moving a high power chip to the next node (with limitation
n cooling and maximum T rise), actually will slow it down

800 900 1000 1100 1200 1300 1400

Peak Frequency (100W/cm2 cooling @ max T 85C) 50 W 72 W 40 W 100 W

No Perf. scaling (Only Shrink) With Performance Scaling

90nm 65nm 45nm 32nm 22nm Performance

Technology

80 W 65 W 50 W 25 W

End of frequency scaling @ ~4 GHz (with 100 W cooling)?

SLIDE 4

System Performance from Multi-Cores

Module Heat Flux(watts/cm2) 2 4 6 8 10 12 14

Vacuum IBM 360 IBM 370 IBM ES9000 IBM 3090S IBM 3090 IBM GP Merced Pentium II(DSIP) Squadrons Pentium 4

Prescott

Low-Power Multi-Core

Bipolar

NMOS / PMOS /CMOS 1950 1960 1970 1980 1990 2000 2010

CMOS CMOS CMOS

Performance Density

SLIDE 5

“Beyond Moore” On-going Trends

Nanoelectronics: Ge, III-V channel to

nanowire/nanotubes and more

Nano-bio/medical: Bio-sensing, imaging
Energy: nanowire solar, nanotube hydrogen

storage

Environmental sensing: Sensor network,

gaseous molecules sensing, ocean, air…

Fusion of nanoelectronics and

nanomechanical: New switches and memories

SLIDE 6

Year 06 07 09 10 11 12 13 14 15 16 08 17 18 19 20 65nm 45nm 32nm 22nm 15nm 10nm 7nm? Flash PCRAM ReRAM MRAM? Strained channel Nanowire devices/nanotubes Molecular devices New channel materials, Ge, III-V Spintronics FERAM Organic/Molecular? 5nm? 193nm+liquid immersion EUV? Self-assembly/bottom up? 2D chip+3D package 3D chip Emerging Bio/Medical Chips Optimistic scenario SOI , FD, UTB

SLIDE 7

High mobility channel Ge and its issues

Advantages

– High electron/hole mobility – Compatibility to Si LSI – Lower temperature process – Possible Vdd scaling

Process and device Issues

1. Poor interface property of Ge MOS gate

Loss of Qch and m degradation

2. Strong Fermi-level pinning at metal/Ge contact

Increase contact resistance

3. Small electron mobility gain

Require mobility booster

4. Poor N-type dopant activation 5. Band-to-band tunneling leakage

0.66 1.12 Band gap (eV, 300K) 1900 430 Hole µ (cm2/Vs) 16 11.9 Dielectric constant 3900 1600 Electron µ (cm2/Vs) Ge Si

S D G 1 3 4 2 5 Ge Si or SiO2 4

SLIDE 8

NMOS Performance Comparison Simulation

S D G G Channel

Gate dielectric LG=15 nm

TOX=0.7 nm VG=0.7V

Si GaAs InP Ge InAs InSb 2 4 6 8

vinj (107cm/s)

10nm 5nm 3nm Si GaAs InP Ge InAs InSb 5 10 15

Qi (1012#/cm2)

10nm 5nm 3nm

Channel Charge (Qi) Injecion Velocity (Vinj) Si high Qi low Vinj III-V low Qi high Vinj Ge reasonably high Qi and Vinj has highest ION Effect of strain is being modeled

Si GaAs InP Ge InAs InSb 1 2 3 4 5 6

ION (mA/µm)

10nm 5nm 3nm

On current (ION)

Kim, Krishnamohan & Saraswat, IEEE DRC 2008

SLIDE 9

Non-silicon high mobility channel approaches

It will fulfill the needs for “higher speed and lower power

consumption”

High mobility materials-gate insulator interface is the

biggest issue

Ge option may provide an opportunity for on-chip optical

interconnect; at least for detector, and maybe for transmitter

Integration density would stay with Si VLSI trend line

(ITRS)

Preferential application on top of the Si platform looks

rational option to go

SLIDE 10

ON/OFF & Bandgap vs. width for GNRs

0.5 0.4 0.3 0.2 0.1 0.0 Eg(eV) 50 40 30 20 10 W (nm) 10 10

1

10

2

103 10

4

10

5

10

6

10

7

Ion/Ioff 50 40 30 20 10 W (nm)

) / exp( /I I

ff
n

T k E

B g

=

( ) ( )

nm W eV Eg 8 . =

All (> 40) sub-10nm GNRs measured thus far are

semiconducting with high on/off switching at 300K

H. Dai, Stanford, 08

SLIDE 11

16 14 12 10 8 6 4 2 Ion(µΑ) 10 10

2

10

4

10

6

Ion/Ioff

Graphene ribbon vs. Carbon Nanotube

GNR w~3nm L~100nm GNR w~2nm L~236nm SWNT d~1.6nm L~102nm SWNT d~1.6nm L~254nm SWNT d~1.3nm L~110nm SWNT d~1.1nm L~254nm

d~1.6nm, L~100nm d~1.6nm, L~250nm d~1.3nm, L~100nm d~1.1nm

High on/off GNR comparable to~1.2nm SWNT FETs GNR FETs comparable to high performance SWNT FETs (d~1.4-1.5nm) remains illusive

H. Dai, Stanford, 08

SLIDE 12

Integration Challenges of CNT, GNR etc

Enough performance advantage over other options as

individual devices

A large variety of tunability for the band structure for a

number of applications

Questions for controlled growth for nanowires and

nanotubes still remain without sacrificing integration density

No top down lithographic technology for the geometry

ranges of GNR

Variability

SLIDE 13

Integration of Electronics into Cells

nanoscale-functionalized probes

at the end of AFM cantilever tips that can directly integrate into a cell membrane.

“stealth electrodes” do not cause

membrane damage, and specifically attach to the core of the lipid bilayer.

future work will involve fabrication
f planar arrays of the devices for
n-chip electrophysiological

measurements.

Professor Nicholas Melosh, Department of Materials Science and Engineering, Stanford University 10 nm Si

Au

A nanoprobe tip. AFM force measurements of the tip interaction with the bilayer. Adhesion force

SLIDE 14

Nanowire Dye-Sensitized Solar-Cells

Dye-sensitized solar cell is one of the most promising third generation solar cells. Using semiconductor nanowires array, as the electron conducting material to replace nanoparticle film, can achieve both a large surface area and a low intrinsic resistance as well as an improved energy conversion efficiency. The idea of this project is: First, using templated Sol-Gel method to grow high aspect ratio and high density TiO2 nanowire array; Secondly, providing bonding of the wire array to a transparent and conductive layer by “after-growth” deposition of materials like ITO onto the back of the nanowire array; Then, dissolving the template following attaching the sample onto a substrate; Finally, this substrate can serve as the anode of the dye-sensitized solar cell. The above nanowire fabrication method can exceed VLS or CVD in aspect ratio and density, and exceed powder based porous array deposition in minimized grain boundaries existing in the electron diffusion paths. Template Nanowires After Dissolving Template Sputtering ITO ITO

Scale bar: 2um

Ying Chen and Yoshio Nishi

SLIDE 15

Summary

A large variety of opportunities in

revolutionary “nano” spaces, from traditional electronics to bio/medical, energy and environment

Manufacturing strategy is still missing and

Opportunities and Challenges for Nanoelectronic Devices and - - PowerPoint PPT Presentation