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OpenSPARC T1 on Xilinx FPGAs Updates Thomas Thatcher Paul Hartke - PowerPoint PPT Presentation

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OpenSPARC T1 on Xilinx FPGAs Updates Thomas Thatcher Paul Hartke Durgam Vahia Paul.Hartke@Xilinx.Com thomas.thatcher@sun.com Xilinx University Program Durgam.Vahia@Sun.com OpenSPARC Engineering RAMP Retreat January 2008,

  1. OpenSPARC T1 on Xilinx FPGAs – Updates Thomas Thatcher Paul Hartke Durgam Vahia Paul.Hartke@Xilinx.Com thomas.thatcher@sun.com Xilinx University Program Durgam.Vahia@Sun.com OpenSPARC Engineering RAMP Retreat – January 2008, Berkeley

  2. Agenda • Quick OpenSPARC Overview • Progress timeline • Current Status > Solaris Boot > Networking > Mapping on Virtex 5 parts > Availability • Roadmap • Q & A 2 www.opensparc.net RAMP Retreat-Jan 2008

  3. Recap: Big Goals • Proliferation of OpenSPARC technology • Proliferation of Xilinx FPGA technology • Make OpenSPARC FPGA friendly > Create reference design with complete system functionality > Boot Solaris/Linux on the reference design > Open it up > Seed ideas in the community Enable multi-core research 3 www.opensparc.net RAMP Retreat-Jan 2008

  4. OpenSPARC T1 • SPARC V9 implementation • Eight cores, four threads each – 32 simultaneous threads • All cores connect through a 134.4 GB/s crossbar switch • High BW 12-way associative 3 MB on-chip L2 cache • 4 DDR2 channels (23 GB/s) • 70W power • ~300M transistors 4 www.opensparc.net RAMP Retreat-Jan 2008

  5. OpenSPARC T1: Some Design Choices • Simpler core architecture to maximize cores on die • Caches, DRAM channels shared across cores • Shared L2 decreases cost of coherence misses significantly • Crossbar good for b/w, latency, and functional verification 5 www.opensparc.net RAMP Retreat-Jan 2008

  6. UltraSPARC-T1 Processor Core ● Four threads per core MUL ● Single issue 6 stage pipeline EXU ● 16KB I-Cache, 8KB D-Cache > Unique resources per thread > Registers > Portions of I-fetch datapath IFU > Store and Miss buffers > Resources shared by 4 threads MMU LSU > Caches, TLBs, Execution Units > Pipeline registers and DP ● Core Area = 11mm2 in 90nm TRAP ● MT adds ~20% area to core Sun Proprietary/Confidential: Internal Use Only

  7. Progress Timeline • RAMP Retreat, July, 2006 > Sun and Xilinx begin OpenSPARC collaboration • RAMP Retreat, January 2007: > Demonstrated OpenSPARC T1 core mapped on ML411 board (XC4VFX100 FPGA) > Ran replays of diagnostic tests • FCRC/RAMP, June 2007: > Demonstrated a stand-alone program running on top of Hypervisor • RAMP Retreat, January 2008 > Demonstrated Solaris running (single user) on the ML411 board 7 www.opensparc.net RAMP Retreat-Jan 2008

  8. Current Status • Solaris Running on ML411-V4FX100 board > Have booted both Solaris 10 and OpenSolaris > Run in single-user mode > Booted from a RAM disk image • Networking functional > Using polled mode > Telnet and FTP are working > Close to having interrupts working • Design is working on Virtex5 board 8 www.opensparc.net RAMP Retreat-Jan 2008

  9. System Block Diagram Xilinx Embedded MultiPort Developer’s Memory FPGA Boundary (EDK) Design Controller External DDR2 Dimm Cache-processor interface (CPX) MCH-OPB MemCon CCX-FSL Microblaze Proc Microblaze Debug UART SPARC T1 Core Interface SPARC T1 UART processor- Fast Simplex 10/100 Ethernet cache interface Links interface (PCX) (FSL) Developed and IBM Coreconnect Working OPB Bus 9 www.opensparc.net RAMP Retreat-Jan 2008

  10. System Operation • OpenSPARC T1 core communicates exclusively via cache-crossbar interface (CCX) > PCX (processor-to-cache), CPX (cache-to-processor) > Glue logic block forwards packets between OpenSPARC core and Microblaze • Microblaze firmware polls T1 core and system peripherals > Services memory and I/O requests > Performs address mapping > Returns results to the core > Maintains coherence of Level-1 caches in OpenSPARC core 10 www.opensparc.net RAMP Retreat-Jan 2008

  11. Software Stack • Out-of-the-box operating system installation • Boots from a virtual disk in Solaris RAM which holds the Open Boot PROM Solaris binaries (OBP) Reset Hypervisor • Able to boot either Code Solaris 10 or OpenSolaris • Entire software stack is open source 11 www.opensparc.net RAMP Retreat-Jan 2008

  12. Solaris Boot 12 www.opensparc.net RAMP Retreat-Jan 2008

  13. Virtex5 Support • Using Xilinx ML505 board with same FPGA as BEE3 > (ugraded 5VLX50T to 5VLX110T) • Synthesis results (no SPU, 16 TLB entries) > 1-thread core: 31475 LUT (45%), 115 BRAM (78%) > 4-thread core: 51558 LUT (74%), 115 BRAM (78%) > Core only, as synthesized by Synplicity • Complete system: > With MicroBlaze core, 2 UART, ethernet, and DDR2 controller: > 1-thread core: 38271 LUT (55%), 128 BRAM (86%) > 4-thread core: 58128 LUT (84%), 128 BRAM (86%) 13 www.opensparc.net RAMP Retreat-Jan 2008

  14. Virtex5 Support • Single-thread core running on ML505-V5LX110T board > Booted Hypervisor > Ran stand-alone application program > Expect to boot Solaris soon • Four-thread core placed and routed. > Booted Hypervisor > Ran stand-alone application program 14 www.opensparc.net RAMP Retreat-Jan 2008

  15. Demo Details • ML411 Board > Solaris Boot on single- thread OpenSPARC T1 > Watch Solaris Boot > Run ancient text-based adventure game > Run Dhrystone MIPS program 15 www.opensparc.net RAMP Retreat-Jan 2008

  16. Demo Details • ML505-V5LX110T Board > Runs a stand-alone C program on top of Hypervisor. > Play the world-famous Dungeon game 16 www.opensparc.net RAMP Retreat-Jan 2008

  17. Roadmap • OpenSPARC T1 Release 1.6 planned for 1Q2008 > EDK project updates > MicroBlaze firmware updates for functionality and performance > ML505-5VLX110T support > Instructions to boot OpenSolaris > Complete reference design for 1-thread and 4-thread cores 17 www.opensparc.net RAMP Retreat-Jan 2008

  18. OpenSPARC momentum Innovation will happen everywhere Innovation Happens Everywhere > 6500 downloads 18 FCRC-RAMP-2007-San Diego www.opensparc.net

  19. Summary • OpenSPARC is a complete microprocessor solution > Complete simulation environment with regression suites > Critical for verifying any changes made to the design > EDK environment demonstrated on Virtex4 and Virtex5 FPGAs > Choice of 1-thread or 4-thread cores > Architectural and simulation models > Hypervisor API • And it's available today! 19 FCRC-RAMP-2007-San Diego www.opensparc.net

  20. Team Ismet Bayraktaroglu Thomas thatcher Durgam Vahia Paul Hartke (Xilinx) Not Pictured: Gopal Reddy 20 www.opensparc.net RAMP Retreat-Jan 2008

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