Serial QDR LVDS High-Speed ADCs on Xilinx Series 7 FPGAs Bruno - - PowerPoint PPT Presentation

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Mar 26, 2023 183 likes •481 views

Serial QDR LVDS High-Speed ADCs on Xilinx Series 7 FPGAs Bruno Valinoti, Rodrigo Melo April 10th to April 12th, 2019, Buenos Aires Outline Introduction ADC board characteristics High Speed ADCs and the evolution next to FPGAs Proposal and

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Serial QDR LVDS High-Speed ADCs on Xilinx Series 7 FPGAs

Bruno Valinoti, Rodrigo Melo April 10th to April 12th, 2019, Buenos Aires

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Outline

Introduction ADC board characteristics High Speed ADCs and the evolution next to FPGAs Proposal and Implementation in the FMC16X IP Core Architecture for testing Validation and Results Conclusions

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Proposed system

◮ Requirements, High speed, SNR and resolution. ◮ Abaco (4DSP) approach & problems ◮ Proposal ◮ Virtex 6 ◮ Zynq7000 series

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Outline

Introduction ADC board characteristics High Speed ADCs and the evolution next to FPGAs Proposal and Implementation in the FMC16X IP Core Architecture for testing Validation and Results Conclusions

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Board specification

FMC164 Analog Inputs Channels 4 Resolution 16 bits Input voltage range 1Vp-p (4dBm) to 2Vp-p (10 dBm) programmable Input gain Programmable from -2dB to 6dB in 0.5dB steps Input impedance 50Ω Analog input bandwidth 500MHz (typical) ADC Output QDR LVDS mode; 4-pairs DDR per channel Output data width DDR LVDS mode; 8-pairs DDR per channel Data Format Offset binary or 2’s complement 250MHz internal clock Sampling Frequency Range Up to 250MHz external clock

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ADC specifications

ADS42LB69 Channels 2 Resolution 16 bits Input voltage range 2-V PP and 2.5-V PP Diff Full-Scale Input Maximum clock rate 250 MSPS SNR 72.3 dBFS @ 230MHz Output Interface DDR or QDR LVDS Input impedance 1.2kΩ (differential)

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Framing features I DDR

N N+1 D0 Clock

D2 D4 D6 D8 D10 D12 D14

2 3 4 5 6 7 8 9 10 11 12 13 14 15

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Framing features II QDR

12 13 14 15 8 9 10 11 4 5 6 7 1 2 3

N N+1 D0 D1 D2 D3 Frame Clock

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Outline

Introduction ADC board characteristics High Speed ADCs and the evolution next to FPGAs Proposal and Implementation in the FMC16X IP Core Architecture for testing Validation and Results Conclusions

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Virtex II and Spartan 3

Scheme used in the application note XAPP774.

IOB

clk

D Q Q Q Q Q Q

D Q0 Q1 Q2 Q3 E Q4 Q5

D Q Q Q Q Q Q

clk_180

D Q0 Q1 Q2 Q3 E Q4 Q5

ena ena_180

Mux & registers

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Virtex 4 and Virtex 5

Scheme used in the application note XAPP866.

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Virtex 6

The application note XAPP1071 shows a more sofisticated scheme:

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Xilinx Series 7

The application note XAPP542 shows a very similar scheme like the XAPP1071.

ISERDESE2 ISERDESE2 ISERDESE2 ISERDESE2

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Outline

Introduction ADC board characteristics High Speed ADCs and the evolution next to FPGAs Proposal and Implementation in the FMC16X IP Core Architecture for testing Validation and Results Conclusions

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Hardware connectios

◮ FMC164 ◮ ZC706 ◮ FMC ◮ DDR vs QDR ◮ framing signals

HA LA LA

K J H G F E D C B A 1 40 LPC & HPC Only HPC

HB HA HB

To get 16-bit values with a sampling clock of 250 MHz, the clock provided by the ADC run at 500 MHz to read 4-bit as DDR two times, known as QDR mode. X Southern Programmable Logic Conference

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IP Modules (I)

◮ adc_data.vhdl ◮ adc_frame.vhdl ◮ adc_cdc.vhdl ◮ adc_clock.vhdl

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IP Modules (II)

◮ IBUFDS: differential input buffer. ◮ IDELAYE2: allows an input signal to be delayed. ◮ IDELAYCTRL: calibrates IDELAYE2, reducing effects of process,

voltage, and temperature variations.

◮ ISERDESE2: a serial-to-parallel converter. ◮ IN_FIFO: very small FIFOs, designed for memory applications but

available as general resource.

◮ ODDR: logic to implement an output DDR register. ◮ BUFG: global clock buffer. ◮ BUFIO: I/O clock buffer. ◮ BUFR: regional clock buffer.

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Data deserializer

IBUFDS x 4 dat_p_i[3:0] dat_n_i[3:0]

ISERDESE2 x 4

D Q5...Q8 CLK CLKDIV BITSLIP clk_i clk_div2_i bitslip_i data_o[15:0] Counter test_i

12 13 14 15 8 9 10 11 4 5 6 7 1 2 3

N N+1 D0 D1 D2 D3 Frame Clock

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Syncronization and CDC (I)

◮ Forced bitslip input ◮ Signal shaping analysis, 1st order derivative ◮ Autoscale trigger ◮ Guard time ◮ Small FIFOs hardblocks near the IO

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Syncronization and CDC (II)

36300 36550 36800 30000 15000 15000 30000 36300 36550 36800 30000 15000 15000 30000 20000 22500 25000 30000 15000 15000 30000 20000 22500 25000 5000 9500 14000

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Clocking

IDELAYE2

IDATAIN DATAOUT CE INC

ISERDESE2

D Q1...Q8 DDLY CLK O CLKDIV

Control FSM

BUFIO BUFR BUFR clk_o clk_div2_o clk_div4 IBUFGDS clk_p_i clk_n_i %2 %4

Different frequencies operating in the system, 500MHz in the IO, 250MHz in data deserialization and 125MHz after the CDC.

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Outline

Introduction ADC board characteristics High Speed ADCs and the evolution next to FPGAs Proposal and Implementation in the FMC16X IP Core Architecture for testing Validation and Results Conclusions

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Design for testing the IP core

test_fmc16x

F M C 1 6 X

a b c d e f g h REGS_to_AXIL AXIL AXIS AXIS axis_data_fifo AXI_DMA AXIL M_AXI_S2MM S_AXIS_S2MM

GP HP

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Top level

In order to be compatible with all the boards of the family, a set of generics are used enabling or disabling the resources by channels groups, depending on the board type.

Core ADS42LB69 Ch A Ch B Ch C Ch D Ch E Ch F Ch G Ch H FMC168 FMC168/4 FMC168/4/2 Core ADS42LB69 Core ADS42LB69 Core ADS42LB69 Ch A Ch B Ch C Ch D Ch E Ch F Ch G Ch H CLK A CLK E CLK A CLK E

DIGITAL ANALOG

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Outline

Introduction ADC board characteristics High Speed ADCs and the evolution next to FPGAs Proposal and Implementation in the FMC16X IP Core Architecture for testing Validation and Results Conclusions

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Validation

◮ An internal fake data generator works muxed with SERDES to test

the system, starting from the fifo’s inputs.

◮ Python scripts to analyze the fake data. ◮ Fast Fourier Transform of a well known signal being sampled.

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Outline

Introduction ADC board characteristics High Speed ADCs and the evolution next to FPGAs Proposal and Implementation in the FMC16X IP Core Architecture for testing Validation and Results Conclusions

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Conclusions

◮ QuADC ◮ Base for the FMC10X IP Core ◮ Packet Standardization

This work was co-funded by the European Union within the European Metrology Programme for Innovation and Research (EMPIR) joint research project 15SIB04 QuADC X Southern Programmable Logic Conference

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INTI-CMNB-FPGA Bruno Valinoti valinoti@inti.gob.ar bruno-valinoti Rodrigo A. Melo rmelo@inti.gob.ar rodrigoalejandromelo @rodrigomelo9ok rodrigomelo9 Attribution-ShareAlike 4.0 International http://creativecommons.org/licenses/ by-sa/4.0/

Questions? Thanks!

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