High Performance ADCs for 5G Benjamin Hershberg imec, Leuven, - - PowerPoint PPT Presentation

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High Performance ADCs for 5G Benjamin Hershberg imec, Leuven, - - PowerPoint PPT Presentation

Oct 16, 2022 114 likes •727 views

High Performance ADCs for 5G Benjamin Hershberg imec, Leuven, Belgium 5G NR FR2: ADC REQUIREMENTS Benjamin Hershberg High Performance ADCs for 5G 2 of 60 5G NR FR2: 3GPP specs 5G Bandwidth Specs Channel: 50MHz, 100MHz, 200MHz, 400MHz

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SLIDE 1

High Performance ADCs for 5G

Benjamin Hershberg imec, Leuven, Belgium

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SLIDE 2

5G NR FR2: ADC REQUIREMENTS

Benjamin Hershberg High Performance ADCs for 5G 2 of 60

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SLIDE 3

 5G Bandwidth Specs ◼ Channel: 50MHz, 100MHz, 200MHz, 400MHz ◼

  • Max. Aggregation:

800MHz ◼ Widest Band: 3.25GHz (24.25GHz – 27.50GHz) ◼

  • Agg. 28GHz Bands: 5.25GHz (24.25GHz – 29.50GHz)

 ...and need >1.5x more bandwidth to relax anti-alias filter.  5G Modulation Specs ◼ QPSK, 16 QAM, 64 QAM, 256 QAM ◼ Future: 1024 QAM

5G NR FR2: 3GPP specs

Benjamin Hershberg High Performance ADCs for 5G 3 of 60

[3GPP , 2019]

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SLIDE 4

 Translation into ADC specs depends heavily on system-level choices

◼ Receiver chain SNR budget ◼ % of standard supported

 Let’s see what we can do across the large range of likely 5G ADC specs:

◼ Resolution: 7 – 13 bits ◼ Speed: 400 MS/s – 12 GS/s ◼ Linearity: 65 dB – 85 dB SFDR (needs to cover Mobile-Terminal, Base-Station, etc...)

5G NR FR2: ADC specs

Benjamin Hershberg High Performance ADCs for 5G 4 of 60

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SLIDE 5

CHANNEL

  • AGG. CHANNEL

BAND

5G NR FR2: ADC SoTA

Benjamin Hershberg High Performance ADCs for 5G 5 of 60

[Murmann, 2019]

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SLIDE 6

Linearity SoTA

Benjamin Hershberg High Performance ADCs for 5G 6 of 60

[Murmann, 2019]

CHANNEL

  • AGG. CHANNEL

BAND

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SLIDE 7

 SFDR/THD specs can be harder than SNR specs!

◼ Noise power gets spread across large bandwidth ◼ Distortion power remains concentrated at specific frequencies

Linearity considerations

Benjamin Hershberg High Performance ADCs for 5G 7 of 60

dB fS1/2 dB fS2/2 dB freq fS1/2 fS2/2 Continuous-time input spectrum: Low speed ADC after sampling: High speed ADC after sampling:

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SLIDE 8

 Beamforming requires many ADCs

◼ Power efficiency ◼ Area efficiency

 Reconfigurability

◼ Large variation in required performance depending on mode (e.g. 50MHz vs. 800MHz BW)

More considerations

Benjamin Hershberg High Performance ADCs for 5G 8 of 60 Vaz ISSCC 2017 Devarajan ISSCC 2017 Straayer ISSCC 2016 Wu ISSCC 2016 Ali VLSI 2016 Architecture Pipe-SAR Pipeline Pipeline Pipeline Pipeline Sampling rate [Gsps] 4 10 4 4 5 Technology [nm] 16 28 65 16 28 ENOB Nyquist [bit] 9.2 8.8 8.9 9.0 9.3 SFDR Nyquist [dB] 67.0 64 64.0 68.0 70 Power [mW] 513 2900 2214 300 2300 FoMWalden [fJ/c.step] 214 631 1130 145 709 FoMSchreier [dB] 153 147 145 154 148 Area [mm²] 1.04 20.2 11.0 0.34 14.4

Industry SoTA

500mW 4GS/s ADC in 0.5mm2 x 128 element digital beam-forming = 64 Watts = 64 mm2 An industrial solution today:

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SLIDE 9

Case Study: MIMO Transceiver

Benjamin Hershberg High Performance ADCs for 5G 9 of 60

 [Jann ISSCC 2019]

◼ First fully-integrated 5G TRX

 Modest ADC specs

◼ 400 MS/s ◼ 7.7 ENOB ◼ ...but ADC is still biggest slice of RX power!

Many ADCs

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SLIDE 10

 High speed (400MS/s - 12GS/s)  Medium resolution (7 - 13b)  High linearity (65dB - 85dB)  Low power  Low area

Conclusions: 5G NR FR2 requirements

Benjamin Hershberg High Performance ADCs for 5G 10 of 60

Industry SoTA can meet these specs... ...but not necessarily with acceptable power / area.

☺ 

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SLIDE 11

GETTING TO GIGA-SAMPLE SPEEDS

Benjamin Hershberg High Performance ADCs for 5G 11 of 60

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SLIDE 12

 Two possible strategies: 1. Fast single-channel

 Practical technology speed limits  Many clocking overheads don’t scale w/ clock  Limited architecture choices

Giga-samples: how do we get there?

Benjamin Hershberg High Performance ADCs for 5G 12 of 60

2 GS/s VIN

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SLIDE 13

 Two possible strategies: 1. Fast single-channel

 Practical technology speed limits  Many clocking overheads don’t scale w/ clock  Limited architecture choices

2. Interleave several slower channels

 Interleave errors (spurs)  Easy to correct: Offset, Gain  Hard to correct: Skew, Bandwidth  Larger input load to drive  Larger area

Giga-samples: how do we get there?

Benjamin Hershberg High Performance ADCs for 5G 13 of 60

2 GS/s VIN

100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s 100 MS/s

VIN

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SLIDE 14

 Combine both strategies

◼ First: maximize channel speed ◼ Then: interleave as necessary

Giga-samples: how do we get there?

Benjamin Hershberg High Performance ADCs for 5G 14 of 60

2 GS/s VIN

1 GS/s 1 GS/s VIN

Core mission statement: Maximize per-channel speed!

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SLIDE 15

 Pipelining

◼ Appears in all medium/high resolution giga-sample ADCs ◼ Break task into smaller pieces ◼ Pass incomplete result along for more processing

 Minimize # of operations in critical timing path

◼ Sample ◼ Quantize ◼ Amplify

Pipelining

Benjamin Hershberg High Performance ADCs for 5G 15 of 60

Stage 2 Stage 1 Stage 3 Stage 4 Backend 3 3 3 3 4 VIN Time Alignment & Digital Error Correction 12 DOUT 3b flash sub-ADC 3 T/H Σ x4 3b sub-DAC VIN VRES DOUT

Example 3b/stage Pipelined ADC

  • 2b/stage of quantization
  • 1b/stage of redundancy (error correction)
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SLIDE 16

Case study: Deep Pipeline

Benjamin Hershberg High Performance ADCs for 5G 16 of 60

 1.5b/stage Flash ADC Quantizer

☺ Fast! Minimum set of actions per stage  Many stages / residue amplifiers [Wu, ISSCC 2016] System 4 GS/s Channel 1 GS/s SNDR 56 dB SFDR 68 dB Power 300 mW FoMW 146 fJ/cs

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SLIDE 17

Case study: Pipelined SAR

Benjamin Hershberg High Performance ADCs for 5G 17 of 60

 SAR as a sub-ADC

☺ Fewer stages / amplifiers ☺ Power efficient sub-ADC  Slower channel speed [Vaz, ISSCC 2017] System 4 GS/s Channel 500 MS/s SNDR 57 dB SFDR 67 dB Power 513 mW FoMW 214 fJ/cs 16nm

Area = 1mm2

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SLIDE 18

 Fast frontend, slower backend

☺ Fast frontend minimizes interleave factor ☺ Interleaved SARs improve backend efficiency  Frontend amplifiers still power-hungry

Case study: Hybrid Pipeline

Benjamin Hershberg High Performance ADCs for 5G 18 of 60

[Brandolini, JSSC 2015] System 5 GS/s Channel 2.5 GS/s SNDR 52 dB SFDR 58 dB Power 150 mW FoMW 96 fJ/cs

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SLIDE 19

AMPLIFICATION: THE HIDDEN BOTTLENECK

Benjamin Hershberg High Performance ADCs for 5G 19 of 60

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SLIDE 20

 Pipelining requires passing along analog residues  To go high speed, you need good amplifiers!

Amplification

Benjamin Hershberg High Performance ADCs for 5G 20 of 60

Stage 2 Stage 1 Stage 3 Stage 4 Backend 3 3 3 3 4 VIN Time Alignment & Digital Error Correction 12 DOUT 3b flash sub-ADC 3 T/H Σ x4 3b sub-DAC VIN VRES DOUT

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SLIDE 21

 Class-A opamps in nanoscale CMOS

 Not enough voltage headroom  Poor efficiency / technology scaling

 Requires a special high-voltage supply

 Eliminates all hope of high efficiency

 But lacking better options, this is still what many in industry use...

Case study: Industry Gigasample ADCs

Benjamin Hershberg High Performance ADCs for 5G 21 of 60

[Ali, JSSC 2014]

2.5V

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SLIDE 22

 Wu, VLSI 2013

◼ 5.4GS/s ◼ 52dB SNDR ◼ 500mW

 Brandolini, JSSC 2015

◼ 5GS/s ◼ 52dB SNDR ◼ 150mW

 Wu, ISSCC 2016

◼ 4 GS/s ◼ 56dB SNDR ◼ 300mW

Case study: Industry Gigasample ADCs

Benjamin Hershberg High Performance ADCs for 5G 22 of 60

  • All 3 ADCs use the same residue amplifier on 1.8V
  • Core circuits on 1.4V/0.4V

[Wu, VLSI 2013] Fs 5.4 GS/s SNDR 52 dB Power 500 mW [Brandolini, JSSC 2015] Fs 5 GS/s SNDR 52 dB Power 150 mW [Wu, ISSCC 2016] Fs 4 GS/s SNDR 56 dB Power 300 mW

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SLIDE 23

 Wu, VLSI 2013

◼ 5.4GS/s ◼ 52dB SNDR ◼ 500mW

 Wu, ISSCC 2016

◼ 4 GS/s ◼ 56dB SNDR ◼ 300mW

 Brandolini, JSSC 2015

◼ 5GS/s ◼ 52dB SNDR ◼ 150mW

Case study: Industry Gigasample ADCs

Benjamin Hershberg High Performance ADCs for 5G 23 of 60

8 high-performance amps 2 high-performance amps 2 high-performance amps 14 low-performance amps [Wu, VLSI 2013] Fs 5.4 GS/s SNDR 52 dB Power 500 mW [Brandolini, JSSC 2015] Fs 5 GS/s SNDR 52 dB Power 150 mW [Wu, ISSCC 2016] Fs 4 GS/s SNDR 56 dB Power 300 mW

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SLIDE 24

Amplification: The Hidden Bottleneck

Benjamin Hershberg High Performance ADCs for 5G 24 of 60

Architectural Freedom Calibration Complexity Power Efficiency Linearity Performance Input Swing High Voltage Supply Amplifier Bottleneck Architectural Freedom Output Swing

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SLIDE 25

 Class-A opamps will never be good in scaled CMOS

◼ Severely constrains ADC design freedoms ◼ 2010’s were the era of the (amplifier-less) SAR ADC

 A new approach is needed!

Conclusions: Amplifier Bottleneck

Benjamin Hershberg High Performance ADCs for 5G 25 of 60

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SLIDE 26

EMERGING AMPLIFICATION SOLUTIONS

Benjamin Hershberg High Performance ADCs for 5G 26 of 60

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SLIDE 27

 Open loop

Gm-C integrator Gm-R amplifier ◼ Charge-pump based

 Feedback

Ring amplifier ◼ Zero-crossing based circuit ◼ Charge-steering amplifier ◼ Digital amplifier

Emerging Amplification Solutions

Benjamin Hershberg High Performance ADCs for 5G 27 of 60

Found in state-of-the-art Gigasample ADCs

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SLIDE 28

Amplifier Wishlist

Benjamin Hershberg High Performance ADCs for 5G 28 of 60

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SLIDE 29

 Basic idea: Integrate current GmVRES onto load capacitor

☺ Fast (open-loop) ☺ Fully dynamic (switchable) ☺ Inherent filtering (sinc) ☺ Good efficiency  Poor linearity  Small input swing  Small output swing  Sensitive to jitter  Sensitive to PVT

Gm-C integrator

Benjamin Hershberg High Performance ADCs for 5G 29 of 60

GmVRES ΦA VRES ΦR VOUT CL

Gm

ΦA tR tA VOUT time Gm · ta CL AV =

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SLIDE 30

Case Study: Gm-C Integrator

Benjamin Hershberg High Performance ADCs for 5G 30 of 60

Channel: Gm-C: [Vaz, ISSCC 2017] System 4 GS/s Channel 500 MS/s SNDR 57 dB SFDR 67 dB Power 513 mW FoMW 214 fJ/cs Tunable integration time:

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SLIDE 31

Gm-R amplifier

Benjamin Hershberg High Performance ADCs for 5G 31 of 60

 Basic idea: RC settle voltage GmVRESRL across load capacitor

☺ Even faster! (no pre-clearing) ☺ Fully dynamic (switchable) ☺ Good efficiency  Moderate PVT sensitivity  Poor linearity  Small input swing  Small output swing

tA VOUT time GmVRES VRES VOUT CL

Gm

ΦA RL

AV = Gm · RL

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SLIDE 32

Case study: Gm-R Amplifier

Benjamin Hershberg High Performance ADCs for 5G 32 of 60

[Jiang, ISSCC 2019] System 1 GS/s Channel 1 GS/s SNDR 60 dB SFDR 75 dB Power 8 mW FoMW 9 fJ/cs  Current SoTA for single-channel gigasample ADCs

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SLIDE 33

CLOAD OUTm INp feedback VDZ

Ring Amplifier

Benjamin Hershberg High Performance ADCs for 5G 33 of 60

 Basic idea: Start in a high efficiency but unstable state and then dynamically stabilize with large-signal feedback [Hershberg, JSSC 2012]

☺ High efficiency ☺ High speed ☺ Wide output swing ☺ Excellent linearity ☺ Scales with digital ☺ Fully dynamic (switchable)  Moderate PVT sensitivity

[Lagos, JSSC 2019] [Lim, JSSC 2015 (1)]

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SLIDE 34

Ring Amplifier

Benjamin Hershberg High Performance ADCs for 5G 34 of 60

CLOAD OUTm INp feedback VDZ

p1 p2 p3 p2  Transient, large signal paradigm  The AC view

◼ Make p1 & p2 as fast as possible

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SLIDE 35

Ring Amplifier

Benjamin Hershberg High Performance ADCs for 5G 35 of 60

CLOAD OUTm INp feedback VDZ

p1 p2 p3 p2  Transient, large signal paradigm  The AC view

◼ Make p1 & p2 as fast as possible ◼ Dynamically reduce p3

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SLIDE 36

Ring Amplifier

Benjamin Hershberg High Performance ADCs for 5G 36 of 60

CLOAD OUTm INp feedback VDZ

p1 p2 p3 p2  Transient, large signal paradigm  The AC view

◼ Make p1 & p2 as fast as possible ◼ Dynamically reduce p3 ◼ ring oscillator → ring amplifier

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SLIDE 37

Ring Amplifier

Benjamin Hershberg High Performance ADCs for 5G 37 of 60

CLOAD OUTm INp feedback VDZ

p3

VOV VOV

 Transient, large signal paradigm  The DC / transient view

◼ VOV initially maximum  Slew-rate at theoretical max. ☺

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SLIDE 38

Ring Amplifier

Benjamin Hershberg High Performance ADCs for 5G 38 of 60

 Transient, large signal paradigm  The DC / transient view

◼ VOV initially maximum  Slew-rate at theoretical max. ☺ ◼ VOV dynamically reduced to adjust P3  Reduces VDSAT → swing/linearity ☺  Increases ro → gain/linearity ☺  Reduces gm → noise filtering ☺

CLOAD OUTm INp feedback VDZ

p3

VOV VOV

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SLIDE 39

[Hershberg, ISSCC 2019 (1)] System 3.2 GS/s Channel 800 MS/s SNDR 63 dB SFDR 80 dB Power 61.3 mW FoMW 19 fJ/cs

Case study: Ring Amplifier

Benjamin Hershberg High Performance ADCs for 5G 39 of 60

VDD DZP EN DZN VSS EN_i EN_i EN EN OUTm INp VDD DZP EN DZN VSS EN_i EN_i EN EN OUTp INm EN VDD EN Vs2p2 Vs2m2 Vs2p1 Vs2m1 VDD VSS MCM2 OUTp

B1

CFB CSMALL CBIG

EN

CSENSE

EN_i EN_i EN_i

Trapped Charge CMFB

Dz_nmos[7:0] 7 VDD DZN EN Dz_pmos[7:0] 7 VSS DZP EN

Trapped-Charge Bias Control

CFB OUTm CSENSE MCM1

 Order-of-magnitude improvement in SoTA  36 ringamps in system

◼ Bottleneck solved?

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SLIDE 40

 Option 1: Design with extra margin

☺ Calibration free  Requires some sacrifice in speed

 Still can achieve SoTA performance

◼ 3 stage ringamp [Lim, JSSC 2015 (2)] ◼ 4 stage ringamp [Lim, VLSI 2017]

Ringamp Robustness Techniques

Benjamin Hershberg High Performance ADCs for 5G 40 of 60

[Lim, JSSC 2015]

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SLIDE 41

 Option 2: Use background tracking

  • r calibration techniques

☺ Optimum performance  Extra analog/digital complexity

Ringamp Robustness Techniques

Benjamin Hershberg High Performance ADCs for 5G 41 of 60

AOL β +

IN OUT X

+- + ‒ v/σ PIPELINE BACKEND “bin” 1 “bin” N

estimator equations

𝐸 𝑊

𝑦

𝐸 𝑊

𝑦

𝐸 𝑊

𝑝𝑣𝑢

bias control VCM v/σ factor estimation

1σ = 0.3 mV

𝑇𝐸𝑆 mean erfinv x mean erfinv x mean erfinv x mean erfinv x

cal ADC

m u x d e m u x 𝐵 𝑃𝑀 𝑇𝐸𝑆 𝑊

𝑃𝑉𝑈, 𝑊 𝑌

𝐵𝑃𝑀 𝑊

𝑃𝑉𝑈, 𝑊 𝑌

[Hershberg, ISSCC 2019 (1)]

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SLIDE 42

 Open-loop where it makes sense

◼ E.g. for very fast amplification

 Ringamps for everything else

◼ Any input swing, any output swing ◼ Any resolution, any speed ◼ All circuits: ADC, VGA, Filter, PLL, etc.

Conclusion: Emerging Amplification

Benjamin Hershberg High Performance ADCs for 5G 42 of 60

GmVRES VRES VOUT CL

Gm

ΦA RL

CLOAD OUTm INp feedback VDZ

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SLIDE 43

DESIGNING FOR RECONFIGURABILITY

Benjamin Hershberg High Performance ADCs for 5G 43 of 60

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SLIDE 44

Wide range of channel bandwidths and modulations:

 5G Bandwidth Specs

◼ Channel: 50MHz, 100MHz, 200MHz, 400MHz ◼

  • Max. Aggregation:

800MHz ◼ Widest Band: 3.25GHz (24.25GHz – 27.50GHz) ◼

  • Agg. 28GHz Bands:

5.25GHz (24.25GHz – 29.50GHz)

 5G Modulation Specs

◼ QPSK, 16 QAM, 64 QAM, 256 QAM ◼ Future: 1024 QAM

➔ A reconfigurable multi-standard ADC is a clear advantage

5G NR FR2 specs revisited

Benjamin Hershberg High Performance ADCs for 5G 44 of 60

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SLIDE 45

 Run-time

Speed ◼ Resolution

 Design-time

Architecture

ADC Reconfigurability

Benjamin Hershberg High Performance ADCs for 5G 45 of 60

= most relevant for 5G

Speed Reconfigurability

[Hershberg, ISSCC 2019 (2)]

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SLIDE 46

 Motivation: constant power efficiency  2 ingredients required

◼ Event-driven control (clocking) ◼ Fully-dynamic power consumption

 Fully-dynamic = no static power  “Next-gen” amplifiers support this

◼ Gm-C ◼ Gm-R ◼ Ringamp

Speed Reconfigurability

Benjamin Hershberg High Performance ADCs for 5G 46 of 60

Ringamp with power-gating function

[Lagos, JSSC 2019]

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SLIDE 47

 Conventional: Synchronous 2-phase non-

  • verlapping clock tree

◼ Simple & effective at lower speeds ◼ But many hidden drawbacks at high speed

 With improvements in amplification tech., clocking becomes the new bottleneck

Event-Driven Control: Deep Pipeline

Benjamin Hershberg High Performance ADCs for 5G 47 of 60

Phase 1 delayed Phase 2 delayed Phase 1 Phase 2

c

INp

STG1

INm

c Local Clkgen STG2 Local Clkgen STG3 Local Clkgen STG4 Local Clkgen STG5 Local Clkgen STG6 Local Clkgen BACKEND Local Clkgen c

master clock

Global Clkgen

[Lagos, CICC 2017]

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SLIDE 48

 Local “Stage Control Units” connected by inter-stage control busses

◼ Communication ◼ Driving local circuits ☺ Correct-by-construction ☺ Minimal global routing ☺ Interleaving advantages ☺ Less sampling jitter ☺ Faster (less timing overhead)

Event-Driven Control: Deep Pipeline

Benjamin Hershberg High Performance ADCs for 5G 48 of 60

[Hershberg, ISSCC 2019 (2)]

VCM 1.5b sub-ADC DOUT[1:0] sub Ringamp +

  • Ringamp

+

  • sub-ADC latch

sample REQ sample REQ

1.5b sub-DAC

track N track early N flush REQ

stage control unit

track early N+1 (ACK) track early N (ACK) flush ACK

stage control unit

STAGE N+1 STAGE N

VCM

STAGE N-1 amplify N sub-ADC latch flush ACK

c

INp

STG1 1.5b CU= 64fF STG2 1.5b CU= 32fF c

master clock

BACKEND 1.5b + 3b CU= 32fF STG3 1.5b CU= 32fF STG4 1.5b CU= 32fF STG5 1.5b CU= 32fF STG6 1.5b CU= 32fF STG7 1.5b CU= 32fF

INm

c

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SLIDE 49

 Internal “chain-reaction” of processing is independent of external clock rate

◼ 1MS/s same as 1GS/s ☺ Enables fully-dynamic operation ☺ Auto maximizes track time ☺ Removes many leakage issues

Event-Driven Control: Deep Pipeline

Benjamin Hershberg High Performance ADCs for 5G 49 of 60

[Hershberg, ISSCC 2019 (2)]

track

quan tize

amplify track track

quan tize

amplify track

. . . . . . . .

track

quan tize

amplify

Conventional clkmax clkmax / 2

track

quan tize

amplify track track

quan tize

amplify track

. . . . . . . .

track

quan tize

amplify

clkmax clkmax / 2 Event-driven

Analog data enters Analog data exits Analog data enters Analog data exits window expands constant

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SLIDE 50

☺ More efficient (less power) ☺ Reconfigurable behavior ☺ No limit to # of clocks/phases  Must be careful about deadlocks  Validation effort increased

Event-Driven Control: Deep Pipeline

Benjamin Hershberg High Performance ADCs for 5G 50 of 60

[Hershberg, ISSCC 2019 (2)]

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SLIDE 51

** Sneak Peek! **  General-purpose solution

◼ Discrete-time comparator-based  [Kull, JSSC 2013] ◼ Can sub-divide into dirty/clean replicas for low-noise and high- accuracy ☺ Low power ☺ General purpose  Still requires some decap area

Fully Dynamic Reference Regulation

Benjamin Hershberg High Performance ADCs for 5G 51 of 60

c c

master clock INm

c

INp

c

VREFP ext.

c

VCM ext.

c

VREFM ext.

VREFP dirty VREFP clean VCM VREFM dirty VREFM clean

reference regulator BACKEND 1.5b + 3b CTOT= 256fF STG1 1.5b CTOT= 256fF STG2 1.5b CTOT= 128fF STG3 1.5b CTOT= 128fF STG4 1.5b CTOT= 128fF STG5 1.5b CTOT= 128fF STG6 1.5b CTOT= 128fF STG7 1.5b CTOT= 128fF

Deep pipeline with dirty/clean reference replicas:

VDD precharge_i

CP

VSS precharge

CM

Charge source / sink

CR

VREF_ext

precharge +

replica out

connect connect_i

Discrete-time regulation circuit:

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SLIDE 52

 Design-time circuit re-use

◼ Faster time-to-market ◼ Less manpower

 Simple, low resolution stages

◼ Use “cheap” high performance amplifiers ◼ Can simply “chain” together using asynchronous, event- driven control protocols

Architecture Reconfigurability

Benjamin Hershberg High Performance ADCs for 5G 52 of 60 STG2 1.5b CU = 128fF STG3 1.5b CU = 64fF STG4 1.5b CU = 32fF BACKEND 9b CU = 32fF

Inventory of low-resolution, fully-dynamic building blocks

BACKEND 9b CU = 32fF 9 c

VIN

STG3 1.5b CU = 64fF c

clk

2 c STG4 1.5b CU = 32fF 2

DOUT

13b ADC (x4) for Base-station Applications [Hershberg, ISSCC 2019 (1)]

STG1 1.5b CU = 200fF

BACKEND 9b CU = 32fF 9 c

VIN

STG2 1.5b CU = 128fF STG3 1.5b CU = 64fF c

clk

2 2 2 c STG1 1.5b CU = 200fF STG4 1.5b CU = 32fF 2

DOUT

11b ADC for Mobile-terminal Applications [Hershberg, ISSCC 2019 (2)]

Easily adapted to many resolution & speed requirements

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SLIDE 53

SUMMARY & CONCLUSION

Benjamin Hershberg High Performance ADCs for 5G 53 of 60

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SLIDE 54

Final Summary

Benjamin Hershberg High Performance ADCs for 5G 54 of 60

1 GS/s 1 GS/s 1 GS/s 1 GS/s 1 GS/s VIN

For best performance at high speeds: First maximize the per-channel speed... ...then interleave as necessary

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SLIDE 55

Final Summary

Benjamin Hershberg High Performance ADCs for 5G 55 of 60

1 GS/s

Pipelining can maximize the per-channel speed

BACKEND 9b CU = 32fF 9 c

VIN

STG2 1.5b CU = 128fF STG3 1.5b CU = 64fF c

clk

2 2 2 c STG1 1.5b CU = 200fF STG4 1.5b CU = 32fF 2

DOUT

But it is amplifier intensive! Luckily, new amplification techniques are now available

CLOAD OUTm INp feedback VDZ

Ringamp

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SLIDE 56

Final Summary

Benjamin Hershberg High Performance ADCs for 5G 56 of 60

ADC Reconfigurability Run-time Constant energy per conversion for multi-standard use Asynchronous- event driven timing control Fully dynamic power use Design-time Building block reuse for reduced design effort Enablers:

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SLIDE 57

Closing the Gap

Benjamin Hershberg High Performance ADCs for 5G 57 of 60

Industry SoTA R&D SoTA

Top Level

CH0 CH1

DOUT[N:0]

CH2 CH3 D0[N:0] D1[N:0] D2[N:0] D3[N:0]

CLKIN

controller

mux

BUF

VIN

BUF

Vaz ISSCC 2017 Devarajan ISSCC 2017 Straayer ISSCC 2016 Wu ISSCC 2016 Ali VLSI 2016 Architecture Pipe-SAR Pipeline Pipeline Pipeline Pipeline Sampling rate [Gsps] 4 10 4 4 5 Technology [nm] 16 28 65 16 28 ENOB Nyquist [bit] 9.2 8.8 8.9 9.0 9.3 SFDR Nyquist [dB] 67.0 64 64.0 68.0 70 Power [mW] 513 2900 2214 300 2300 FoMWalden [fJ/c.step] 214 631 1130 145 709 FoMSchreier [dB] 153 147 145 154 148 Area [mm²] 1.04 20.2 11.0 0.34 14.4 Hershberg ISSCC 2019 e Pipeline s] 3.2 ] 16 t] 10.0 ] 73.3 ] 61 ] 19 ] 166 ²] 0.194

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SLIDE 58

References (1)

Benjamin Hershberg High Performance ADCs for 5G 58 of 60

3GPP, 2019 3GPP, “5G NR release 15”, 2019. [Online]. Available: https://www.3gpp.org/release-15 Ali, JSSC 2014

  • A. M. A. Ali et al., "A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration," in IEEE Journal of

Solid-State Circuits, vol. 49, no. 12, pp. 2857-2867, Dec. 2014. Brandolini, JSSC 2015

  • M. Brandolini et al., "A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in

28 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2922-2934, Dec. 2015. Hershberg, ISSCC 2019 (1)

  • B. Hershberg et al., "3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of

Distortion," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 58-60. Hershberg, ISSCC 2019 (2)

  • B. Hershberg et al., "3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven

Clocking in 16nm," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 68-70. Hershberg, JSSC 2012

  • B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita and U. Moon, "Ring Amplifiers for Switched

Capacitor Circuits," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2928-2942, Dec. 2012. Jann, ISSCC 2019

  • B. Jann et al., "21.5 A 5G Sub-6GHz Zero-IF and mm-Wave IF Transceiver with MIMO and Carrier

Aggregation," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019,

  • pp. 352-354.

Jiang, ISSCC 2019

  • W. Jiang, Y. Zhu, M. Zhang, C. Chan and R. P. Martins, "3.2 A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-

Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, Kull, JSSC 2013

  • L. Kull et al., "A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for

Enhanced Speed in 32 nm Digital SOI CMOS," in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3049- 3058, Dec. 2013.

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SLIDE 59

References (2)

Benjamin Hershberg High Performance ADCs for 5G 59 of 60

Lagos, CICC 2018

  • J. Lagos, B. Hershberg, E. Martens, P. Wambacq and J. Craninckx, "A 1Gsps, 12-bit, single-channel pipelined ADC

with dead-zone-degenerated ring amplifiers," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, 2018, pp. 1-4. Lagos, JSSC 2019

  • J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq and J. Craninckx, "A 1-GS/s, 12-b, Single-Channel Pipelined

ADC With Dead-Zone-Degenerated Ring Amplifiers," in IEEE Journal of Solid-State Circuits, vol. 54, no. 3, pp. 646- 658, March 2019. Lim, JSSC 2015 (1)

  • Y. Lim and M. P. Flynn, "A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring

Amplifiers," in IEEE Journal of Solid-State Circuits, vol. 50, no. 10, pp. 2331-2341, Oct. 2015. Lim, JSSC 2015 (2)

  • Y. Lim and M. P. Flynn, "A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted

Pipeline ADC," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2901-2911, Dec. 2015. Lim, VLSI 2017

  • Y. Lim and M. P. Flynn, "A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring

amplifier based SAR-assisted pipeline ADC," 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C98-C99. Murmann, 2019

  • B. Murmann, "ADC Performance Survey 1997-2019," [Online]. Available:

http://web.stanford.edu/~murmann/adcsurvey.html. Vaz, ISSCC 2017

  • B. Vaz et al., "16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC," 2017 IEEE

International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 276-277. Wu, ISSCC 2016

  • J. Wu et al., "A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS," 2016 IEEE

International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 466-467. Wu, VLSI 2013

  • J. Wu et al., "A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS," 2013 Symposium on VLSI Circuits, Kyoto,

2013, pp. C92-C93.