Continuous Time Sigma Delta Modulators and VCO ADCs Pieter Rombouts - - PowerPoint PPT Presentation
Continuous Time Sigma Delta Modulators and VCO ADCs Pieter Rombouts Electronics and Information Systems Lab., Ghent University, Belgium Pavia, March 2017 P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 1 / 80 Outline Sigma
Electronics and Information Systems Lab., Ghent University, Belgium
CTSDMs and VCO ADCs Pavia 2017 1 / 80
1
2
3
4
5
CTSDMs and VCO ADCs Pavia 2017 2 / 80
◮ quantisation step q:
◮ static nonlinearity ◮ INL or DNL
CTSDMs and VCO ADCs Pavia 2017 3 / 80
◮ (white) noise signal ◮ like other noise contributions ◮ number of bits not essential ⋆ large enough
Leave margin for other noise sources
⋆ effective bits
Q = q2
CTSDMs and VCO ADCs Pavia 2017 4 / 80
spectrum spectrum 0.1 0.2 0.3 0.4 0.5 signal white noise 0.1 0.2 0.3 0.4 0.5 frequency/fsample frequency/fsample
CTSDMs and VCO ADCs Pavia 2017 5 / 80
spectrum spectrum 0.1 0.2 0.3 0.4 0.5 signal white noise 0.1 0.2 0.3 0.4 0.5 frequency/fsample frequency/fsample
◮ averaging mechanism ◮ number of bits has increased ◮ less noise ◮ filters signal as well ⋆ not Nyquist-rate anymore!
CTSDMs and VCO ADCs Pavia 2017 6 / 80
spectrum spectrum 0.1 0.2 0.3 0.4 0.5 signal white noise 0.1 0.2 0.3 0.4 0.5 frequency/fsample frequency/fsample
Q =
CTSDMs and VCO ADCs Pavia 2017 7 / 80
+ +
D Q
DAC
◮ discrete time ◮ continuous time
CTSDMs and VCO ADCs Pavia 2017 8 / 80
+ +
D Q
DAC
CTSDMs and VCO ADCs Pavia 2017 9 / 80
1 1+H ≈ 0
1 1+H = 0
CTSDMs and VCO ADCs Pavia 2017 10 / 80
NTF(z) DC
freq.
fsample/2 1
1 1+H = 0
CTSDMs and VCO ADCs Pavia 2017 11 / 80
(a) (b)
DC
freq.
fsample/2 DC
freq.
fsample/2 signal shaped noise
CTSDMs and VCO ADCs Pavia 2017 12 / 80
+ +
D Q
DAC
◮ very few bits ◮ accuracy from oversampling + noise shaping ◮ 1 bit
CTSDMs and VCO ADCs Pavia 2017 13 / 80
+ +
D Q
DAC
◮ simple ◮ inherent linear ◮ noise is not white ⋆ tones ⋆ stability
CTSDMs and VCO ADCs Pavia 2017 14 / 80
+ +
D Q
DAC
◮ better performance ◮ DAC needs linearization ⋆ DEM ⋆ calibration ◮ always larger area
CTSDMs and VCO ADCs Pavia 2017 15 / 80
+ +
D Q
DAC
◮ cascade of integrators ◮ order: design parameter ⋆ trade-off complexity-performance ◮ special design techniques ⋆ Richard Schreier’s toolbox
CTSDMs and VCO ADCs Pavia 2017 16 / 80
Typical circuit
bi
C
D Q clk
◮ also C ◮ (thermal) noise ↓ due to oversampling
CTSDMs and VCO ADCs Pavia 2017 17 / 80
Cascade of integrators with feedback
DAC 1 z -1 b2 1 z -1 c2
b3 b4
c3 u(n) v(n) y(n) x3(n) x2(n 1 z -1 b1 c1 x1(n)
◮ high swing on internal nodes ◮ ‘poor’ distortion performance
CTSDMs and VCO ADCs Pavia 2017 18 / 80
Cascade of integrators with feedforward
DAC 1 z -1 b2 1 z -1 c3
b3 b4 a3 u(n) v(n) y(n) x3(n) x2(n 1 z -1 b1 c2 x1(n)
a2 a1
◮ negligible swing on internal nodes ◮ excellent distortion performance
CTSDMs and VCO ADCs Pavia 2017 19 / 80
Sigma Delta modulator
lowpass filter
Vin anti-aliasing
prefilter
f < f
cutoff S
fS 2f0 Dout f = f
cutoff
analog digital decimation filter
◮ simple anti-aliasing filter ◮ no sample-to-sample correspondence
CTSDMs and VCO ADCs Pavia 2017 20 / 80
Sigma Delta modulator
lowpass filter
Vin anti-aliasing
prefilter
f < f
cutoff S
fS 2f0 Dout f = f
cutoff
analog digital decimation filter
◮ without filters ◮ accuracy calculated from ideal filter
CTSDMs and VCO ADCs Pavia 2017 21 / 80
◮ keep fs feasable ◮ need many quantizer bits ◮ need high order filter ◮ minimum 8
◮ small devices ⋆ noise is filtered ◮ low filter order ◮ 1-bit quantiser
CTSDMs and VCO ADCs Pavia 2017 22 / 80
1
2
3
4
5
CTSDMs and VCO ADCs Pavia 2017 23 / 80
◮ oversampling and noise shaping ◮ high-accuracy
CTSDMs and VCO ADCs Pavia 2017 24 / 80
◮ versatile ◮ “simple” design ◮ easy to “abuse”
◮ potential for higher speed ◮ potential for lower power ◮ anti-aliasing ◮ non-trivial design (needs tuning) ◮ performance and stability depend on fclk ◮ common myth: sensitive to clock jitter
CTSDMs and VCO ADCs Pavia 2017 25 / 80
Vin(s) fs Dout(z) ZOH(s) ZOH(s) a1 sTs aN sTs
◮ cascade of integrators with feedback ◮ cascade of integrators with feedforward . . .
CTSDMs and VCO ADCs Pavia 2017 26 / 80
Linearized model
Vin(s) fs Dout(z) ZOH(s) ZOH(s) a1 sTs aN sTs
◮ Input signal ◮ Quantisation noise
CTSDMs and VCO ADCs Pavia 2017 27 / 80
...
f s Dout(z) ZOH(s) ZOH(s) a1 sTs aN sTs
...
−
Σ Σ
−
Σ
−
Σ Q
−
Σ
ZOH(s) H(s) f s Heq(z) Dout(z)
Q
◮ fully equivalent ◮ impulse invariant transform of H(s) ◮ CT - DT relationship: z = esTclk
CTSDMs and VCO ADCs Pavia 2017 28 / 80
−
Σ
ZOH(s) H(s) f s Heq(z) Dout(z)
Q
CTSDMs and VCO ADCs Pavia 2017 29 / 80
−
Σ
ZOH(s) H(s) f s Heq(z) Dout(z)
Q
◮ theory = mature ⋆ e.g. c2d function in matlab ◮ Heq depends on Dac-pulse ◮ Heq depends on fs ◮ Heq sensitive to analog imperfections ⋆ ‘excess’ loop delay ⋆ parasitic (opamp) poles
CTSDMs and VCO ADCs Pavia 2017 30 / 80
Linearized model
Vin(s) fs Dout(z) ZOH(s) ZOH(s) a1 sTs aN sTs
◮ Input signal ◮ Quantisation noise
CTSDMs and VCO ADCs Pavia 2017 31 / 80
V
in(s)
f s Dout(z) ZOH(s) ZOH(s) a1 sTs aN sTs
V
in(s)
Dout(z) G(s) f s
ZOH(s) H(s) f s Heq(z)
CTSDMs and VCO ADCs Pavia 2017 32 / 80
V
in(s)
Dout(z) G(s) f s
−
Σ
ZOH(s) H(s) f s Heq(z)
V
in(s)
D
G(s) f s V
in(s)
D
G(s) f s
AAF(s) NTF(z) NTF(z)
CTSDMs and VCO ADCs Pavia 2017 33 / 80
◮ G(S) lowpass filter ◮ NTF(z) notches at nfclk
CTSDMs and VCO ADCs Pavia 2017 34 / 80
2−8 2−7 2−6 2−5 2−4 2−3 2−2 2−1 20 21
50 f/fs Amplitude response (dB) NTFeq(esTs) G(s) AAF(s) N = 2 a1 = 0.3246 a2 = 0.6667
CTSDMs and VCO ADCs Pavia 2017 35 / 80
Vin(s) fs Dout(z) ZOH(s) ZOH(s) a1 sTs aN sTs
◮ double anti-aliasing: G(s) and NTF ⋆ less stringent prefiltering requirements ◮ large internal signal swing ⋆ more demanding opamps ◮ ADC itself = power hungry but system may be more
CTSDMs and VCO ADCs Pavia 2017 36 / 80
Vin
+ a1 sT quant an sT T H (s)
DAC
a2 sT D
◮ single anti-aliasing: NTF but G(s) does not filter ⋆ stringent pre-filtering requirements ◮ small internal signal swing ⋆ no demanding opamps ◮ ADC itself = efficient but system may be power hungry
CTSDMs and VCO ADCs Pavia 2017 37 / 80
Vin
+ a1 sT quant an sT T H (s)
DAC
a2 sT D
◮ later stages scaled ⋆ lower power ⋆ still negligible noise
◮ increasing order ⇒ moderate impact on power
CTSDMs and VCO ADCs Pavia 2017 38 / 80
n = 4kTReff · B
◮ only in band noise ◮ no kT/C noise
CTSDMs and VCO ADCs Pavia 2017 39 / 80
CTSDM problems
Vin
+ a1 sT quant an sT T H (s)
DAC
a2 sT D
CTSDMs and VCO ADCs Pavia 2017 40 / 80
CTSDM problems Σ
c1 sTs
− Vin(s)
Σ
c2 sTs c3 sTs
a3
Σ
fs Vout(z) a2 a1 d HDAC(s) z−1 z− 1
2
− g e−sτ HDAC(s)
◮ make loop delay explicit ◮ add compensation path
CTSDMs and VCO ADCs Pavia 2017 41 / 80
CTSDM problems Σ
c1 sTs
− Vin(s)
Σ
c2 sTs c3 sTs
a3
Σ
fs Vout(z) a2 a1 d HDAC(s) z−1 z− 1
2
− g e−sτ HDAC(s)
◮ tune ◮ robust design
CTSDMs and VCO ADCs Pavia 2017 42 / 80
CTSDM problems
◮ multi-bit ◮ some filtering (e.g. FIR)
CTSDMs and VCO ADCs Pavia 2017 43 / 80
CTSDM problems Σ
c1 sTs
− Vin(s)
Σ
c2 sTs c3 sTs
a3
Σ
fs Vout(z) a2 a1 d HDAC(s) z−1 z− 1
2
− g e−sτ HDAC(s)
◮ directly affects performance ◮ depends on DAC pulse
CTSDMs and VCO ADCs Pavia 2017 44 / 80
CTSDM problems
clock
ZOH
clock
ZOH ZOH
◮ catastrophical ◮ solution: multi-bit, FIR etc.
◮ no big deal
CTSDMs and VCO ADCs Pavia 2017 45 / 80
◮ inherent anti-aliasing ⋆ no noise aliasing
cfr kT/C noise in switched cam
⋆ better power-noise trade off ◮ common myth ⋆ sensitive to clock jitter
⇒ not as bad as widely assumed
◮ facts ⋆ performance and stability depend on fclk ⋆ non-trivial design
CTSDMs and VCO ADCs Pavia 2017 46 / 80
1
2
3
4
5
CTSDMs and VCO ADCs Pavia 2017 47 / 80
◮ difficult to compare ADC architectures ◮ different Peak SNDR, Power, Bandwidth, Technology,
◮ which architecture for new design?
CTSDMs and VCO ADCs Pavia 2017 48 / 80
◮ pJ/conversion code (or pJ/conversion step) ◮ intended to reduce variables ◮ no justification ◮ used for many years ◮ but meaningless . . .
CTSDMs and VCO ADCs Pavia 2017 49 / 80
◮ OK
◮ ???
CTSDMs and VCO ADCs Pavia 2017 50 / 80
◮ OK if comparator power
◮ comparator power ∼ 2N ◮ comparator power ∼ 22N
Vin + + + +
D D D Q Q Q Q clk clk clk clk
Vref 1 1 1
CTSDMs and VCO ADCs Pavia 2017 51 / 80
I R (a) W L C V 2I R/2 2W L 2C V (b)
◮ scale impedances: factor 2
CTSDMs and VCO ADCs Pavia 2017 52 / 80
CTSDMs and VCO ADCs Pavia 2017 53 / 80
◮ not used
CTSDMs and VCO ADCs Pavia 2017 54 / 80
1
2
3
4
5
CTSDMs and VCO ADCs Pavia 2017 55 / 80
+ + + + + +
Ctrl N stages
Vdd Ctrl W 2W
main inverters aux inverters
4x 4x 1x 1x
vin+ vin- vout- vout+
◮ ring oscillators ◮ ‘digital’ signals ◮ no opamps
CTSDMs and VCO ADCs Pavia 2017 56 / 80
in
kv fc
f s f s f s f s
fVCO fs
◮ e.g. 6-bit for fs = 1GHz, fVCO = 64GHz,
CTSDMs and VCO ADCs Pavia 2017 57 / 80
VCO1 V
in
reset counter
kv fc
D
f s f s f s f s
VCO1 V
in
counter
kv fc
D
f s f s
I
1 - z-1 D
CTSDMs and VCO ADCs Pavia 2017 58 / 80
VCO1 V
in
counter
kv fc
D
f s f s
I
D VCO1
in
quant
kv fc
D
f s f s
I
D V
in
kv fc
D
s s I
D
in
1/s
kv fc
D
s
f s
I
1 - z-1 D + 1 - z-1
CTSDMs and VCO ADCs Pavia 2017 59 / 80
V
in
kv fc
D
f s f s
I
D
in
1/s
kv fc
D
f s f s
I
D + + Q 1 - z-1
◮ anti-aliasing ◮ noise shaping ◮ boost accuracy by oversampling
CTSDMs and VCO ADCs Pavia 2017 60 / 80
+ + + + + +
Ctrl N stages
Vdd Ctrl W 2W
main inverters aux inverters
4x 4x 1x 1x
vin+ vin- vout- vout+
◮ ring oscillator has N output phases
◮ now phase transition at 2π/N ◮ quantization error: N times smaller ◮ higher effective number of bits
CTSDMs and VCO ADCs Pavia 2017 61 / 80
◮ use parallelism
CTSDMs and VCO ADCs Pavia 2017 62 / 80
VCO V
in
reset counter D
f s f s f s f s
reset counter
f s f s f s f s
reset counter
f s f s f s f s
adder
◮ equivalent fs = 1GHz, fVCO = 64GHz, ◮ 6-bit
CTSDMs and VCO ADCs Pavia 2017 63 / 80
VCO V
in
reset counter D
f s f s f s f s
reset counter
f s f s f s f s
reset counter
f s f s f s f s
adder
◮ special case: 1 bit counter ◮ possible if fVCO ≤ fs
CTSDMs and VCO ADCs Pavia 2017 64 / 80
clk D Q
VCO[i] DFF
clk D Q ^
Dout
^
fs
+1 +1 +1
> <
(a) (b)
VCO3 CLK
Dout TS
> <
TS t t t
> <
TS
◮ effectively fVCO,eff = 2fVCO
CTSDMs and VCO ADCs Pavia 2017 65 / 80
ff w2(t) D Q D Q fs D Q D Q fs D Q D Q fs wM(t) w1(t) x(t)
y[n] M-phases ring oscillator Readout circuit (xM)
CTSDMs and VCO ADCs Pavia 2017 66 / 80
ff w2(t) D Q D Q fs D Q D Q fs D Q D Q fs wM(t) w1(t) x(t)
+
... ...
y[n] M-phases ring oscillator Readout circuit (xM)
◮ inherent DWA ◮ can drive unit element DAC ◮ summation = ‘thermometer to binary” coder
CTSDMs and VCO ADCs Pavia 2017 67 / 80
ff w2(t) D Q D Q fs D Q D Q fs D Q D Q fs wM(t) w1(t) x(t)
+
... ...
y[n] M-phases ring oscillator Readout circuit (xM)
◮ 0 < fVCO < fs/2
◮ free running fVCO,0 = fs/4 ◮ KV for full scale swing ◮ some tuning
CTSDMs and VCO ADCs Pavia 2017 68 / 80
◮ current research
CTSDMs and VCO ADCs Pavia 2017 69 / 80
◮ prototype in 65 nm CMOS ◮ 12bits@10MHz (with digital calibration) ◮ 11bits@10MHz (without digital calibration) ◮ 3.5 mW ◮ 0.01 mm2
CTSDMs and VCO ADCs Pavia 2017 70 / 80
◮ best: 11-bit linearity (UGent) ◮ other solutions ⋆ digital (self)-calibration ⋆ swing reduction ⋆ embed in Sigma Delta Loop
CTSDMs and VCO ADCs Pavia 2017 71 / 80
ring oscillator VCO non-linearity
+ + + + + +
Ctrl N stages
Ring-Osc
Vin Ctrl R1 R2 Vdd
CTSDMs and VCO ADCs Pavia 2017 72 / 80
ring oscillator VCO non-linearity
0.2 0.4 0.6 0.8 1 100 150 200 250 300 350 400 450 500
(a) Input voltage [volt] VCO Frequency [MHz]
0.2 0.4 0.6 0.8 1 −3 −2 −1 1 2 3
(b) Input voltage [volt] VCO Frequency error [MHz]
CTSDMs and VCO ADCs Pavia 2017 73 / 80
ring oscillator VCO non-linearity
non-linearity
noise-shaping modulator digital non-linearity correction
decimation
in
◮ nonlinearity is smooth ◮ can be very small (11 points excellent results)
CTSDMs and VCO ADCs Pavia 2017 74 / 80
ring oscillator VCO non-linearity
VCO reset counter f s
kv , fc
+ − V
in
ADCf DACf + Dout(z)
◮ aux ADC and DAC ⋆ uncritical ◮ sensitive to mismatch
CTSDMs and VCO ADCs Pavia 2017 75 / 80
ring oscillator VCO non-linearity
VCO reset counter Dout(z) f s
kv , fc
loop filter +
V
in
◮ Original work by Perrott’s group ◮ input signal of VCO still large
◮ 3rd order noise shaping ◮ 2nd order suppression of VCO nonlinearity
CTSDMs and VCO ADCs Pavia 2017 76 / 80
VCO in feedback loop
VCO2
kv , fc
VCO1
kv , fc
Vin +
+
kv , fc
VCO1
kv , fc
+
+
f s
sampler
Dout(z) + − DAC V
in
◮ pseudo differential
◮ can be largely digital
CTSDMs and VCO ADCs Pavia 2017 77 / 80
VCO in feedback loop
VCO2
kv , fc
VCO1
kv , fc
+
+
f s
sampler
Dout(z) + − DAC V
in
◮ pseudo differential
◮ can be largely digital ◮ can be multi-phase
CTSDMs and VCO ADCs Pavia 2017 78 / 80
ring oscillator VCO non-linearity
VCO2
kv , fc
VCO1
kv , fc
+
+
f s
sampler
Dout(z) DAC loop filter +
in
◮ 3rd order noise shaping ◮ input signal of VCO small ◮ 3rd order suppression of VCO nonlinearity
CTSDMs and VCO ADCs Pavia 2017 79 / 80
Review of
1
2
3
4
5
CTSDMs and VCO ADCs Pavia 2017 80 / 80