SLIDE 1
Outline
- Introduction to FPGAs and Xilinx System Generator
- System Generator basics
- Fixed point binary numbers
- Fixed point arithmetic
- Sample times
- Tips for building models
Introduction to Xilinx System Generator Part I Evan Everett and - - PowerPoint PPT Presentation
Introduction to Xilinx System Generator Part I Evan Everett and - - PowerPoint PPT Presentation
Introduction to Xilinx System Generator Part I Evan Everett and Michael Wu ELEC 433 - Spring 2013 Outline Introduction to FPGAs and Xilinx System Generator System Generator basics Fixed point binary numbers Fixed point
SLIDE 2
SLIDE 3
FPGA Basics: Architecture
SLIDE 4
FPGA Basics: Architecture
Configurable Logic Blocks Block RAM I/O Buffers Digital Clock Manager Multiplier
Switch Matrix Slice Slice Slice Slice SLIDE 5
Switch Matrix
Slice Slice Slice Slice
FPGA Basics: Architecture
Slice Configurable Logic Block
Lookup Tables (LUTs) implement any 4-input logic function
LUT LUT
MUX MUX
Register Register
Misc Logic
SLIDE 6
FPGA Basics: Glossary
- LUT: lookup table
- MUX: multiplexer
- MULT: embedded multiplier
- Slice: atomic logic block containing 4 LUTs and 8 flip flops
- DSP Slice: slice containing an adder, accumulator and multiplier
- CLB: configurable logic block
- BRAM: block random access memory
SLIDE 7
FPGA Basics: Resources
Device Slices DCMs Mults 18 Kb BRAMs I/O Virtex-2 Pro XC2VP50 Virtex-4 XC4VFX100 Virtex-6 LX240T Virtex-7 XC7VX415T 23,316 8 232 232 852 42,176 12 160 376 768 37,680 12 768 832 720 63,400 12 2,160 1,760 600
Example Resources for Xilinx Virtex family FPGAs
SLIDE 8
FPGA Basics: Resources
Device Slices DCMs Mults 18 Kb BRAMs I/O Virtex-2 Pro XC2VP50 Virtex-4 XC4VFX100 Virtex-6 LX240T Virtex-7 XC7VX415T 23,316 8 232 232 852 42,176 12 160 376 768 37,680 12 768 832 720 63,400 12 2,160 1,760 600
Example Resources for Xilinx Virtex family FPGAs
v3 uses this chip
SLIDE 9
How do we target these resources?
- Hardware description languages (HDL) like Verilog/VHDL
allow designers to specify at a higher level than logic gates
- We will use an even higher level tool called
System Generator
- Graphical programming environment within Matlab’s Simulink
SLIDE 10
System Generator Basics
- System Generator provides two key tools
- Blocks for building your model
- Hardware generator: model → HDL
- Simulink provides a test environment for your design
- Generate test vectors with MATLAB or Simulink blocks
- Visualize and analyze output of design
- Leverage MATLAB expressions within design
- Simulation and hardware will match “bit true” and “cycle true”
SLIDE 11
System Generator
MATLAB Simulink SysGen Generate
VHDL
Xilinx Blocks
sin(0:1024./pi) fir(10,0.2)
Bit True
SLIDE 12
System Generator Example
- Simulink blocks are your signal sources and sinks
- Xilinx blocks are your to-be-synthesized FPGA design
Simulink Blocks Simulink Blocks
Xilinx Blocks
SLIDE 13
System Generator Example
- These will be realized in hardware
System Generator Blocks
SLIDE 14
System Generator Example
- Configures simulation & hardware parameters
- Relates sample period to hardware clock
- Used to synthesize model
- Sets target FPGA device for model
System Generator Token
SLIDE 15
System Generator Example
- Must be outside System Generator gateways
- Operate on floating point values
- Good for data sources & analysis
- Source: continuous-time floating point constant
- Sink: signal vs. time scope
Simulink Blocks
SLIDE 16
System Generator Example
- Convert between floating and fixed point values
- Top-level ports in HDL model
- Must set precision & sample rate in Gateway In
Gateway Blocks
SLIDE 17
System Generator Basics
- Every model needs a System Generator token
- Models start and end with Gateway blocks
- : double to fixed point conversion
- : fixed point to double conversion
- Any Simulink blocks can be used outside gateways
- Good for data sources and output analysis
- Only Xilinx blocks can be used inside gateways
- Synthesis treats gateways as top-level ports
System Generator