NoC System Generator A tool for fast prototyping of multi-core - - PowerPoint PPT Presentation

NoC System Generator

A tool for fast prototyping of multi-core systems on FPGAs Francesco Robino, Johnny ¨ Oberg, Hosein Attarzadeh, Ingo Sander

KTH Royal Institute of Technology

FPGAworld 2013

• F. Robino (KTH)

NoC System Generator 10-09-2013 1 / 7

Motivation: Embedded systems modeling

Embedded systems are getting very complex We want to abstract, reduce details in the system model We want System Design Automation to automatically add details

it implements the embedded application on multi-processor platforms the automated synthesis of the whole system must be fast!

• F. Robino (KTH)

NoC System Generator 10-09-2013 2 / 7

Motivation: Embedded system architecture

Embedded architectures are getting very complex details are increasing! sea-of-cores / processors NoC-based MPSoC

Pe0 Pe2 Pe3 Pe6 Pe5 Pe8 Pe9 Pe11 Pe1 Pe4 Pe7 Pe10

• F. Robino (KTH)

NoC System Generator 10-09-2013 3 / 7

The problem(s)

P e P e P e P e P e P e

Huge abstraction gap

How to automate (and speed up) the process?

Huge design space

How to explore it?

Platform:

How to program it? How to instantiate it?

Filling the gap through design automation: benefits

Reduces time to market, reduces errors, reduces designer’s effort...

• F. Robino (KTH)

NoC System Generator 10-09-2013 4 / 7

Proposed solution: the NoC System Generator tool

The NoC System Generator generates a complete multi-core/processor system targeted for FPGA solutions from high-level description of the application and the platform An intuitive GUI permits to:

model the embedded system software as interconnected C process model the embedded system platform explore different mapping of processes on the platform

Processors in the platform can be selected from a range of industry accepted soft-cores, connected through a NoC:

NiosII, Leon3, uBlaze, HW accelerators

Integration with Xilinx Platform Studio and Altera QSYS, permitting to target and switch between both vendors

• F. Robino (KTH)

NoC System Generator 10-09-2013 5 / 7

The NoC System Generator flow

Platform model Application model

NoC System Generator

C XML

+ SW generation: .c and .h files for each processor HW generation:

• Altera QSYS

(*.sopc, *.qsys, etc)

• Xilinx XPS

(*.mhs, *.mss, etc)

NoC .vhd files Scripts for Altera and Xilinx tools

XML: HW description Application processes binding C: SW functionality Processes synchronization P e P e P e P e P e P e

• F. Robino (KTH)

NoC System Generator 10-09-2013 6 / 7

Results and conclusions

1 Reduce the design time for instantiation and prototyping of a

fully configurable and heterogeneous NoC-based MPSoC.

Target platform Generate architecture model Generate Xilinx/Altera project 4 processors ∼100 milliseconds ∼500 milliseconds

2 Automatically generate HW and SW sources and program the

NoC-based MPSoC on FPGA.

3 Explore the design space of multiple HW and SW configurations

through a intuitive GUI.

4 Support for soft and firm real-time systems.

More info, related papers and tutorials

https://forsyde.ict.kth.se/noc generator/

• F. Robino (KTH)

NoC System Generator 10-09-2013 7 / 7