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MIPS Datapath CMSC 301 Prof Szajda Goal Build an architecture to - PowerPoint PPT Presentation

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MIPS Datapath CMSC 301 Prof Szajda Goal Build an architecture to support the following instructions w Arithmetic: add, sub, addi, slt w Memory references: lw, sw w Branches: j, beq Process 1) Design basic framework that is needed by all

  1. MIPS Datapath CMSC 301 Prof Szajda

  2. Goal • Build an architecture to support the following instructions w Arithmetic: add, sub, addi, slt w Memory references: lw, sw w Branches: j, beq

  3. Process 1) Design basic framework that is needed by all instructions 2) Build a computer for each operation individually 3) Add MUXs to choose between different operations 4) Add control signals to control the MUXs

  4. MIPS Steps • Get an instruction from memory using the Program Counter (PC) • Read one or two registers each instruction w One register: addi, lw w Two registers: add, sub, slt, sw, beq • All instructions use ALU after reading regs • Some instructions also access Memory • Write result to Register file

  5. Framework Get instruction from memory

  6. Framework Get Read instruction from from register memory file

  7. Framework Use ALU Get Read instruction from from register memory file

  8. Framework Use ALU Get Read Access instruction from memory from register memory file

  9. Framework Use ALU Get Read Access instruction from memory from register memory file Write register file

  10. Get Instruction Where do we store instructions?

  11. Get Instruction Where do we store instructions? Memory Data Address Instruction Memory

  12. Get Instruction How do we know at what address to fetch instruction? Data Address Instruction Memory

  13. Get Instruction How do we know at what address to fetch instruction? Program Counter Program Counter Data (PC) Instruction Memory

  14. Get Instruction What do we end up with? Program Counter Data (PC) Instruction Memory

  15. Get Instruction What do we end up with? Instruction Program Counter Instruction (PC) Instruction Memory

  16. Get Instruction What happens to the PC each instruction? Program Counter Instruction (PC) Instruction Memory

  17. Get Instruction What happens to the PC each instruction? Increment by 4B 4 Program Counter Instruction (PC) Instruction Memory

  18. “Add” Instruction Use ALU Get Read instruction from from register memory file Write register file

  19. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 4 Read Use ALU from register op/fun PC file Read Addr rs Out Data rt Instruction rd Inst Memory imm Write register file

  20. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How many registers do we need to read? 4 Use ALU op/fun PC Read Addr rs Out Data Instruction rt Register File rd Memory Inst imm Write register file

  21. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How many registers do we need to read? 2 4 Use ALU op/fun PC Read Addr rs Out Data Instruction rt Register File rd Memory Inst imm Write register file

  22. “Add” Instruction Operation rs rt rd shamt funct # meaning What part of add 3 5 2 0 32 # $2 <- $3 + $5 instruction tells us the register number? 4 Use ALU op/fun src1 src1data PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst imm Write register file

  23. “Add” Instruction Operation rs rt rd shamt funct # meaning What part of add 3 5 2 0 32 # $2 <- $3 + $5 instruction tells us the register number? 4 rs & rt Use ALU op/fun src1 src1data PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst imm Write register file

  24. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 4 op/fun src1 src1data PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst imm Write register file

  25. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How do we know which 4 register to write? src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst imm destdata

  26. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How do we know which 4 register to write? src1 src1data op/fun rd PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  27. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  28. What happens if instruction reads and writes same register? Operation rs rt rd shamt funct # meaning add 3 5 3 0 32 # $3 <- $3 + $5 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  29. What happens if instruction reads and writes same register? Operation rs rt rd shamt funct # meaning add 3 5 3 0 32 # $3 <- $3 + $5 What would happen if we allowed write to occur at any time? Clock is dependent on longest path (lw) 4 Quick operations may loop twice through machine, getting incorrect result. src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  30. Reading/Write Registers • When does register get written? w At the end of the clock cycle w Edge-triggered circuits

  31. “Addi” Instruction Operation rs rt imm # meaning What addi $5,$3,6 3 5 6 # $5 <- $3 + 6 registers do we read? 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  32. “Addi” Instruction Operation rs rt imm # meaning What addi $5,$3,6 3 5 6 # $5 <- $3 + 6 registers do we read? rs 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  33. “Addi” Instruction Operation rs rt imm # meaning Where do addi $5,$3,6 3 5 6 # $5 <- $3 + 6 we get the second input? 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  34. “Addi” Instruction Operation rs rt imm # meaning addi $5,$3,6 3 5 6 Where do we # $5 <- $3 + 6 get the second input? 4 imm (16 bits ) src1 src1data op/fun PC Read Addr rs Out Data src2 src2data rt Instruction Register File rd Inst Memory destreg imm destdata 32 bits 16 bits

  35. Sign Extension • How do we go from 16-bit number to 32-bit number? • How about 4-bit to 8-bit. w 0111 = 7 = 00000111 w 1110 = -2 = 11111110 • Take the top bit and copy it to all the other bits

  36. “Addi” Instruction Operation rs rt imm # meaning Sign extend addi $5,$3,6 3 5 6 # $5 <- $3 + 6 immediate value 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  37. “Addi” Instruction Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6 How do we know which 4 register to write? src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  38. “Addi” Instruction Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6 How do we know which 4 register to write? src1 src1data op/fun rt PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  39. Putting them Together 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  40. Putting them Together Two wires to the same input 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  41. Putting them Together Two wires to the same input Add MUXs 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  42. Putting them Together What determines which to take? 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  43. Putting them Together What Control determines Unit ALUOp which to take? Op/Func code ALUSrc 4 RegDest src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

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