[PPT] - ECE232: Hardware Organization and Design Lecture 11: Introduction to PowerPoint Presentation

SLIDE 1

Adapted from Computer Organization and Design, Patterson & Hennessy, UCB

ECE232: Hardware Organization and Design

Lecture 11: Introduction to MIPs Datapath

SLIDE 2

ECE232: Intro to MIPs Datapath 2

MIPS-lite processor

Want to build a processor for a

subset of MIPS instruction set (“MIPS-lite”)

just enough to illustrate key

ideas

instruction set subset (3

groups):

arithmetic-logical:

add, sub, and, or, slt

memory reference: lw, sw
control flow: j, beq
can we write real programs

with just these?

Need up to 5 steps to execute any

instruction in our subset Processor (CPU) Computer Control Datapath IMemory MIPS Instructions DMemory

SLIDE 3

ECE232: Intro to MIPs Datapath 3

Instruction Execution Steps

Instruction Fetch Decode, Inc PC and Read Registers ALU Operation, Branch address Data Memory

peration

Write Back

1. Read IM[PC]
2. Instruction Decode, PC = PC + 4,

Register read

3. ALU operation, Branch address

computation

4. LW/STORE in Data memory
5. Register Write

SLIDE 4

ECE232: Intro to MIPs Datapath 4

Building a Datapath for MIPS (step 1)

PC Instruction Memory

Step 1    add $t0,$t0,$t0

add $t0,$s1,$t0

lw $t1,20($s0) sw $t1,4($t0)   . . .

PC-4

PC

PC+4 PC+8

. . Flow of execution Step 1: instruction fetch

SLIDE 5

ECE232: Intro to MIPs Datapath 5

Datapath Step 1: Any Instruction

PC Instruction Memory (IMem) Address Instruction A d d “4” 32-bit adder

r ALU

wired only for add Clock Once program is loaded, IMem is read-only

SLIDE 6

ECE232: Intro to MIPs Datapath 6

Building a Datapath for MIPS (step 2)

PC Registers Step 1 Step 2: Decode and Read Registers add $t0,$s1,$t0 Instruction Memory

p rs rt rd shamt funct

0 17 8 8 0 32 R

SLIDE 7

ECE232: Intro to MIPs Datapath 7

Datapath Step 2: Any Instruction

Register File

Read Register 1 Read data 1 Read data 2 Read Register 2 Write Register Write Data

Instruction

Control

Datapath Control Points

6

p rs rt rd shamt funct

R add $t0,$t1,$t2

SLIDE 8

ECE232: Intro to MIPs Datapath 8

Remaining Steps in Executing Instructions

3rd step onwards depends on instruction class
EX: for ALU instructions: add $t0, $t1, $t2
utputs from registers t1 and t2 will be sent to the ALU input
For Memory-reference instruction:

lw $t0,20($s0) Address  Base + offset A L U

SLIDE 9

ECE232: Intro to MIPs Datapath 9

Building a Datapath for MIPS (lw step 3)

PC Registers A L U Instruction Memory Step 1 Step 2 Step 3

p rs rt address

lw $t0, 20($s0) I

SLIDE 10

ECE232: Intro to MIPs Datapath 10

Datapath Step 3-4: R-format Instructions

Registers

Read Register 1 Read data 1

A L U

Read data 2 Read Register 2 Write Register Write Data

Instruction Result

Zero

ALU control 3 32

RegWrite

add, sub, and, or

[$t1] [$t2] [$t1]  [$t2] { +, -, AND, OR, etc.} [$t3] [$t1]  [$t2]

SLIDE 11

ECE232: Intro to MIPs Datapath 11

Datapath Step 3: Branch

Registers

Read Register 1 Read data 1

A L U

Read data 2 Read Register 2 Write Register Write Data

Instruc- tion Zero

RegWrite Sign Extend

32 16 A d d Branch target To branch control logic PC + 4 from step 1 datapath

Mult by 4

beq $t0,$t1,loop

ALU control

3 Result [$t0] [$t1]

SLIDE 12

ECE232: Intro to MIPs Datapath 12

Steps 4,5 in Executing lw,sw

4th step depends on instruction class
Ex: for lw: Fetch Data from Memory

Data  Mem[Address]

For sw: Put the contents of a register in Memory

From Register for SW

To register for LW

lw $t1,20($s0) sw $t1,4($t0)

PC Registers A L U

Step 1

Step 2 Step 3 Data Memory Step 4 Instruction Memory

5th step only for lw; rest are done
for lw: Write Result

Reg[rt]  Data

SLIDE 13

ECE232: Intro to MIPs Datapath 13

Datapath Step 3-5: Load/Store

Registers

Read Register 1 Read data 1

A L U

Read data 2 Read Register 2 Write Register Write Data

Instruc- tion

Zero

ALU control

RegWrite Address Read data Write Data Sign Extend

32 16

DMem

MemRead MemWrite

lw $t0,24($s3)

p rs rt address

Result [$s3] “24”

[$s3]+24

SLIDE 14

ECE232: Intro to MIPs Datapath 14

Compose Datapath: R-form + Load/Store

Registers

Read Register 1 Read data 1

A L U

Read data 2 Read Register 2 Write Register Write Data

Instruction Zero ALU control 3

RegWrite Address Read data Write Data Sign Extend

32 16

DMem

MemRead MemWrite 1

M u x

MemTo- Reg

0=R-form 1=L/S

M u x

ALUSrc

0 = R-format 1 = Load/Store

Add muxes

SLIDE 15

ECE232: Intro to MIPs Datapath 15

Compose Datapath: + IMem + PC

Registers

Read Reg1 Read data1

A L U

Read data2 Read Reg2 Write Reg Write Data

Zero ALU control 4

RegWrite

Address Read data Write Data Sign Extend

32 16

DMem

MemRead MemWrite M u x MemTo- Reg M u x ALUSrc

Read Addr Instruc- tion

IMem

“4” P C a d d

SLIDE 16

ECE232: Intro to MIPs Datapath 16

Compose Datapath: + Branch

Registers

Read Reg1 Read data1

A L U

Read data2 Read Reg2 Write Reg Write Data

Zero

ALUcon RegWrite

Address Read data Write Data Sign Extend

32 16

DMem

MemRead MemWrite

M u x

MemTo- Reg

M u x

ALUSrc Read Addr Instruc- tion

IMem

“4” P C a d d

a d d << 2 M u x

PCSrc “Left Shift 2” module

Supports all MIPS-lite instructions? (slt and ?)

SLIDE 17

ECE232: Intro to MIPs Datapath 17

Datapath: Register fields

Destination registers may differ across instruction formats:
R-format:

[rd]  [rs] op [rt] add $t0,$s0,$s1 For this instruction, bits 11-15 are the destination (t0), which should be connected to the write reg. inputs

I-format:

[rt]  mem[[rs] + imm16] lw $t0,24($s3) For this instruction, bits 16-20 should go to the write reg.

port. Bits 0-15 go to the ALU as address
Connection to the write reg. port changes!
Solution? mux to the rescue!
p

rs rt rd funct shamt

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

p

rs rt

ffset

6 bits 5 bits 5 bits 16 bits

SLIDE 18

ECE232: Intro to MIPs Datapath 18

Datapath (add RegDst Mux)

Regs

Read Reg1 Read data1

A L U

Read data2 Read Reg2 Write Reg Write Data

Zero

ALU- con RegWrite

Address Read data Write Data

Sign Extend

DMem

MemRead MemWrite

M u x

MemTo- Reg

M u x

Read Addr Instruc- tion

IMem

4 P C a d d a d d << 2

M u x

PCSrc ALU- src

M u x

25:21

20:16 15:11

RegDst

15:0

31:0

SLIDE 19

ECE232: Intro to MIPs Datapath 19

Datapath: Determine next PC

What if instruction is a conditional branch (beq)?
if operands equal, take branch (PC gets PC+4+offset)
else PC gets PC+4
Therefore, set control point PCSrc = 1 if and only if beq and

Zero asserted

SLIDE 20

ECE232: Intro to MIPs Datapath 20

Datapath (add Branch control point)

Regs

Read Reg1 Read data1

A L U

Read data2 Read Reg2 Write Reg Write Data

Zero

ALU- con RegWrite

Address Read data Write Data

Sign Extend

DMem

MemRead MemWrite

M u x

MemTo- Reg

M u x

Read Addr Instruc- tion

IMem

4 P C a d d a d d << 2

M u x

ALU- src

M u x

25:21 20:16 15:11

RegDst 15:0

31:0

Branch

PCSrc

SLIDE 21

ECE232: Intro to MIPs Datapath 21

Summary

Clear understanding of ENGIN112 components is necessary
Review memories, registers, multiplexers, and ALUs, if necessary
The MIPs processor is built from the description of MIPs instructions
How do we physically execute each instruction?
Identify components that will perform the execution
Share the components
In this implementation, an “instruction execution” starts with the PC

and ends with the completion of the instruction

For example, add two values from registers and write the value back to a

register

Don’t get left behind
Today’s material is critical to the next five weeks of the course