[PPT] - Microelectronics l for Radiation Detectors Gianluigi De Geronimo PowerPoint Presentation

SLIDE 1

Electrical and Computer Engineering

l Microelectronics for Radiation Detectors

Gianluigi De Geronimo

gianluigi.degeronimo@stonybrook.edu, degeronimo@ieee.org

Lawrence Berkeley National Laboratory December 20th, 2016

SLIDE 2

Outline Outline

Introduction
Introduction
Charge Amplification in CMOS
Charge Amplification in CMOS
Evolution of FE ASICs
Evolution of FE ASICs
Conclusions
Conclusions

2

SLIDE 3

Sources of Electronic Noise Sources of Electronic Noise

El i i

reset

CF Electronic noise: from components directly connected to input node

reset

v(t)

Sv

K(f,τ)

connected to input node

Q∙δ(t)

Si CS CG

   

f K 1 f H

verall transfer function

   

    , f K fC 2 j 1 , f H

F

need minimum 2 poles!

 

2 2 G S 2 v 2 i

df ) f ( H C C S df ) , f ( H S

 

 

   

 

2 max 2

t h ENC

 



Time‐variant → me‐domain analysis (noise weighting function)

3

SLIDE 4

10

14

Noise from Input Transistor Noise from Input Transistor

10

15

Sv [V²/Hz]

1/f

w f v

g A f C A S  

CG intrinsic gate capacitance

proportional to the gate size

10

17

10

16

ectral density

1/f hi

m G

g f C

CG = CS (capacitive matching)

p p g

10

18

Noise spe

white

G S (

p g)

10

1

10

2

10

3

10

4

10

5

10

6

10

7

10

19

Frequency f [Hz]

   

G 2 G S G w w G 2 G S f f 2 v

C C C C g A a C C C A a ENC     

From input transistor:

S C i

G G m G

C C g C 

ASIC: power constraints

ƒTmax (max current) ƒT

4

SLIDE 5

Input Transistor in CMOS Input Transistor in CMOS

 

2

C C A

F i '

Fix power = fix

   

G 2 G S G D m w w 2 vw

C C C C I g A a ENC   

From transistor's white noise:

Fix power fix drain current ID → size (W,L) ?

VGS >> Vth (strong inversion) VGS << Vth (weak inversion)

→ ( , )

 

2 D G D

x

D m

L I C I L W n µc 2 I g  

 

D T D D m

I nV I I g   load

 

2 G S 2

C C L ENC  

 

2 G S 2

C C ENC  

↓ ↓ VGS

G D vw

C I ENC 

 

D G S vw

I ENC 

minimum L
independent of L

GS

minimum L
CG = CS/3

independent of L

CG = 0 pushes back towards

strong inversion

→ VGS ≈ Vth (moderate inversion): model?

5

SLIDE 6

Moderate Inversion Moderate Inversion

gm [mS] IC 1 d k IC=1 moderate strong weak ID [mA]

 

IC 2 1 IC 4 1 nV I I g

D D m

    

x

2 T D

µc nV 2 I W L IC 

From EKV model

IC 2 nVT 

inversion coefficient

De Geronimo, IEEE TNS 52, 2005

alternative: extract from simulators (BSIM)

6

SLIDE 7

Gate Capacitance Gate Capacitance

C [pF]

2

n‐MOS p‐MOS CG [pF]

2Wcov+2/3coxWL

n‐MOS p‐MOS

coxWL

IC=1

 CoxWL

1 overlap

h l

10

3 

 0 01 0 1 1 10 100

ID [mA]

bulk channel

 

 

            ) IC ( 1 n 1 n ) IC ( WL C W c 2 I C

C C

x
v

D G

10  0.01 0.1 1 10 100

3 / 2 2 C

IC 1 IC 4 1 3 1 2 3 ) IC (



             

  n

IC 3 2    

Both g and CG push towards using n‐channel and L = L

i

Both gm and CG push towards using n channel and L = Lmin

7

De Geronimo, IEEE TNS 52, 2005

SLIDE 8

10

14

Low‐Frequency Noise Low‐Frequency Noise

10

15

10

14

/Hz]

w f v

A A S  

w f

A A S  

10

16

10

sity Sv [V²/

m G v

g f C

m G v

g f C S 



10

17

ectral dens

n‐MOS

10

18

Noise spe

p‐MOS

10

2

10

3

10

4

10

5

10

6

10

7

10

19

Frequency f [Hz]

 

2 G S 2

C C 

 

2 G S f 2

C C A ) ( ENC 

depends

From transistor's

 

G G S f f 2 vf

C C C A a ENC  

 

G G S 1 f f 2 vf

C ) ( a ENC   

 

depends

n τ

From transistor s low‐freq. noise:

8

SLIDE 9

Low‐Frequency Noise vs L Low‐Frequency Noise vs L

100

]

CMOS 180nm, IC=1 n-MOS

nt Afeq [a.u.

 

w f

A L A S  

10

0.3 at 3xLmin

se coefficie

m G v

g f C S  



1

0.6 at 2xLmin p-MOS

quency nois

1/f i l t I TNS 58 2011

180 270 360 450 540 0.1

Low freq

1/f equivalent, IEEE TNS 58, 2011

  



2

180 270 360 450 540

Channel length [nm]

  



G 2 G S 1 f f 2 vf

C C C L A ) ( a ENC    

 

From transistor's low‐freq. noise:

LF noise pushes towards p‐channel & L > Lmin

9

SLIDE 10

Discharge Network (Reset) Discharge Network (Reset)

RF

dc stabilization
discharge of C

C

RF

reset

discharge of CF

S CF

v(t)

Sv

K(f,τ)

‐∞

Q∙δ(t) Si

CS CA

 

i 2 iR

R kT 4 a ENC

F

F i iR

R

F

kT 4

S F

qI 2 R kT 4  ) mV 50 (~ q 2 kT 4 I R

S F



"50mV rule"

sensor shot noise

from leakage current IS

examples CZT: IS = 1nA → RF >> 50 MΩ Si: IS = 1pA → RF >> 50 GΩ

10

SLIDE 11

Reset in CMOS Reset in CMOS

linear region saturation
linear region ?

RF ?

MF VG

noise

self‐adjusts to IS

     

TH GS m M i

V V qI 2 V V kTg 4 S

F

RF ?

MF C IS

j

S

 

TH GS S

V V qI 2

F

CF

S

v(t)

Sv

K(f,τ)

‐∞

IS

Q∙δ(t)

Si CS CA

1 m TH GS

V 40 kT q I g V V at



   

use large L, small W to push

S

kT I

MF towards strong inversion

Noise at discharge ?

11

SLIDE 12

Reset in CMOS ‐ Discharge Noise Reset in CMOS ‐ Discharge Noise

VG

Q/C

CF MF

Q/C

MF noise increases at discharge

Sv CF

‐∞

τ

Q∙δ(t)

Si CS CA

‐∞

τd

t

i 2

Q 2 a ENC   

use large τ /τ

d i 2 id

qQ 2 2 ENC   

use large τd/τ

De Geronimo, NIM A 421, 1999

At high rate     qQ 2 a ENC

i 2

V

At high rate  τd decreases    qQ 2 2 ENCidr

t alternative: use MF as switch or adopt time‐variant discharge t

12

SLIDE 13

Reset in CMOS ‐ Pole Linearity Reset in CMOS ‐ Pole Linearity

MF VG V CF MF

∞ Q∙δ(t) CS+CA ‐∞

τd

t

τd depends on amplitude and may affect baseline y H t li li l ll ti ? How to realize a linear pole‐zero cancellation ?

13

SLIDE 14

Reset in CMOS ‐ Pole‐Zero Cancellation Reset in CMOS ‐ Pole‐Zero Cancellation

VG non‐linear linear 1st stage of filter C MF

G

RS N×M VG RS

Q∙δ(t)

CF N×CF N×MF

G

CS

Q∙δ(t) CS+CA ‐∞

N CF

‐∞

~N×Q∙δ(t)

2 R i

kT 4 S  filter noise contribution:

2 S R i

N R S

S

te

se co t but o

Effective linear "charge amplification" by N

De Geronimo, IEEE TNS 47, 2000

14

SLIDE 15

Delayed Dissipative Feedback (DDF)

delay feedback of dissipative element (i.e. resistor RS ) Q∙N RS CS CF C N CS Q∙N V1

‐∞

Q CF∙N

‐∞

ther poles

Vout Q charge gain N shaper DDF shaper

high analog dynamic range

DRa DRa ≈ Qmax Qmax ENC +ENC ENC +ENC

g g y g

a

ENCca+ENCsh ENCca+ENCsh

15

De Geronimo, IEEE TNS 58, 2011

SLIDE 16

Front‐End ASIC for X‐Ray Spectrometers Front‐End ASIC for X‐Ray Spectrometers

10

6

10

55Fe, T = -44 C

Peaktime 1 µs Rate 1 kcps 50 Msamples

Mn K FWHM = 145 eV (~10e-)

10

6

10

4

50 Msamples

Ch. 14

s 10

5

Rate = 200 kcps

55Fe, T = -44 C

Peaktime = 1 µs 50 Msamples

Ch. 9

Mn K FWHM = 180 eV

e V 1 F W H M

i d r

 

10

2

Count 10

4

FWHM = 1 7 FWHM

Ch. 9

nts 10 no PUR 10

2

10

3

FWHM2 = 1.7 FWHM (efficiency ~ 0.6) no PUR Coun 10 1 2 3 4 5 6 7 8 9 PUR 10

1

PUR

ASIC for x‐ray spectroscopy

16 ch 2 1x4 6mm² 1mW/ch

Energy [keV] 10 3 6 9 12 15 18 Energy [keV]

ASIC functions charge amplifier

16 ch., 2.1x4.6mm², 1mW/ch.

Collaboration with NASA De Geronimo, IEEE TNS 57, 2010

Energy [keV]

charge amplifier, shaper, discriminator, peak detector, pile‐up rejector, amplitude/address multiplexer

SLIDE 17

Circuits in a Front‐End ASIC Circuits in a Front‐End ASIC

Low‐noise, low‐power charge amplifiers
gas, liquid, solid state detectors
capacitances from ~ fF to ~ nF
Switched and continuous adaptive reset
High‐order filters, stabilizers, drivers
peak time / gain adjustment
Single‐ and multi‐level discriminators

g

Peak and time detectors, derandomizers
Analog memories and multiplexers
Digital memories and counters
Digital memories and counters
Configuration registers
ESD protections

C lib i l

64‐ch. VMM ASIC ATLAS Muon Upgrade 14x8.5 mm², ~0.4W/cm²

Calibration pulse generators
Analog‐to‐digital converters
Digital‐to‐analog converters

, / > 6M MOSFETs (> 90k/ch.), 2016

Precision band‐gap references
Temperature sensors
Readout control logic
Digital signal processing (DSP)
Low‐voltage differential signaling (LVSD, SLVS)

Pace of FE ASIC Evolution?

SLIDE 18

VMM (2012‐16) for P1 Muon Upgrade VMM (2012‐16) for P1 Muon Upgrade

ll h l ATLAS Muon New Small Wheels

‐ sTGC and MicroMegas technologies 2 3M channels 50 to 2000 pF ‐ 2.3M channels, 50 to 2000 pF

r

neighbor ART (flag + serial address) ART clock logic

r

ART (flag + serial address) d t /TGC l k TGC out (ToT, TtP, PtT, PtP, 6bADC) 64 channels data1 CA shaper

6‐b ADC 10‐bADC

peak data/TGC clock DSP analog1 data2 analog2

10 b ADC 8‐b ADC

time 4X FIFO mux test DSP analog2 addr.

12‐b BC

tk clock trim test analog mon. Gray count BC clock logic tk clock pulser bias registers tp clock temp DAC reset prompt

18

SLIDE 19

Physical Layout

400 i custom 400‐pin 21 x 21 mm² BGA

13.5 mm 13.5 mm 1.5 mm 1.5 mm 300 µm 300 µm 70 µm 70 µm 15 µm 15 µm 5 µm 5 µm

manual place & route ~ 400 bonding pads fabrication at commercial foundries packaging wirebonding

SLIDE 20

Impact on Radiation Detector Impact on Radiation Detector

2005 ‐ ASM 2015 ‐ VMM

60x sensing elements, 10x element density, 3x power dissipation
data‐driven, trigger primitives, peak, timing, ADCs, DSP, ...

2005 ASM 2015 VMM

, gg p , p , g, , ,

Advances in radiation detectors are ti htl l d t d i f t d ASIC Advances in radiation detectors are ti htl l d t d i f t d ASIC tightly coupled to advances in front‐end ASICs tightly coupled to advances in front‐end ASICs

Front‐end ASICs are rapidly becoming very Front‐end ASICs are rapidly becoming very

t e d

S Cs a e ap d y beco g e y high functionality systems‐on‐chip (SOC)

t e d

S Cs a e ap d y beco g e y high functionality systems‐on‐chip (SOC)

20

SLIDE 21

Gamma spectrometer

Designers

Evolution of Front‐End ASICs Evolution of Front‐End ASICs

1 ‐ 2

~ year 2001 CMOS 500nm, 3.3V, ~2mm² ~ 10k transistors (~100/ch) preamplifier/filter Gamma spectrometer Compton imager ATLAS upgrade

Designers Years Revisions Simul time 1 2 1 ‐ 2 1 ‐ 2 1m/ch

preamplifier/filter ~ 2006 250nm, 2.5V, 25mm² ATLAS upgrade

Simul. time 1m/ch

~ 100k transistors (1k/ch) + discrim/peakdet/count/mux ~ 2011

2 ‐ 4 2 ‐ 4 2 4

2011 130nm, 1.2V, 50mm² ~ 1M transistors (~ 10k/ch) + timedet/multifunc/trigprim

2 ‐ 4 1h/ch

~ 2016 to 2020 < 90nm, < 1.2V, >100mm² > 10M transistors (>100k/ch)

> 5 3 ‐ 5

> 10M transistors (>100k/ch) + ADCs+DSP SOC = System on Chip EOC = Experiment on Chip

3 ‐ 5 >1d/ch

VMM is 90k!

Complexity and functionality are rapidly increasing

SLIDE 22

The Rapid Evolution of Microelectronics The Rapid Evolution of Microelectronics

10µ

L 1 µ m 1 2 V first MOSFET

10G 100G 10µ

> 3GHz Xbox One 28nm L 10 µm 12V first MOSFET 5V

10G 100G 1µ 10µ

ength L

100M 1G

rs / die

1µ 10µ

800nm 5V 6-core I7 45nm 10-core XEON 32nm V 1 5V m 1.8V 250nm 2.5V 500nm 3.3V 1.2µm 5V

ength L

3µm 5V

100M 1G

rs / die

100n

hannel le

1M 10M

ransistor

100n

32nm 1.1V nm 0.9V 45nm 1.1V Intel 80486 4nm FinFET 0.7V 28nm 1.0V 65nm 1.2V 90nm 1.2V 130nm 1.5 180nm 1 250 5

hannel le

1M 10M

ransistor

10n

sistor ch

10k 100k 1M

mber of tr

10n

3 20nm Intel 80286 Intel 80486 16-14n 28n

sistor ch

10k 100k 1M

mber of tr

1n

1MHz first IC Intel 4004

Trans

1k 10k

Num

1n

first IC

Trans

1MHz Intel 4004

1k 10k

Num

1960 1970 1980 1990 2000 2010 2020 2030 2040

Year

100 1960 1970 1980 1990 2000 2010 2020 2030 2040

Year

100

22

SLIDE 23

The Rapid Evolution of Microelectronics The Rapid Evolution of Microelectronics

10µ

> 3GHz Xbox One 28nm L 10 µm 12V first MOSFET 5V

10G 100G 1µ 10µ

800nm 5V 6-core I7 45nm 10-core XEON 32nm V 1 5V 1.8V 250nm 2.5V 500nm 3.3V 1.2µm 5V

ength L

3µm 5V

100M 1G

rs / die

Exotic Transistors

single‐electron
carbon‐nanotube
...

Exotic Transistors

single‐electron
carbon‐nanotube
...

100n

32nm 1.1V nm 0.9V 45nm 1.1V Intel 80486 4nm FinFET 0.7V 28nm 1.0V 65nm 1.2V 90nm 1.2V 130nm 1.5 180nm 1 250 5

hannel le

1M 10M

ransistor

... ... 10n

32 20nm Intel 80286 Intel 80486 16-14n 28n

sistor ch

10k 100k 1M

mber of tr

1n

Si lattice spacing 0.54nm first IC

Trans

1MHz Intel 4004

1k 10k

Num

1960 1970 1980 1990 2000 2010 2020 2030 2040

Year

100

Introduced in the ’90s, exotic transistors made considerable progress, but are still far from achieving reproducibility and reliability required for microelectronics

23

SLIDE 24

3D (FF) + 3D

The Rapid Evolution of Microelectronics The Rapid Evolution of Microelectronics

10µ

Through-Si Vias (TSV) 3D (FF) + 3D 3D 2.5D > 3GHz Xbox One 28nm L 10 µm 12V first MOSFET 5V

10G 100G

TSV TSV

1µ 10µ

800nm 5V 6-core I7 45nm 10-core XEON 32nm V 1 5V 1.8V 250nm 2.5V 500nm 3.3V 1.2µm 5V

ength L

3µm 5V

100M 1G

rs / die

Exotic Transistors

single‐electron
carbon‐nanotube
...

Exotic Transistors

single‐electron
carbon‐nanotube
...

100n

32nm 1.1V nm 0.9V 45nm 1.1V Intel 80486 4nm FinFET 0.7V 28nm 1.0V 65nm 1.2V 90nm 1.2V 130nm 1.5 180nm 1 250 5

hannel le

1M 10M

ransistor

... ... 10n

32 20nm Intel 80286 Intel 80486 16-14n 28n

sistor ch

10k 100k 1M

mber of tr

1n

Si lattice spacing 0.54nm first IC

Trans

1MHz Intel 4004

1k 10k

Num

1960 1970 1980 1990 2000 2010 2020 2030 2040

Year

100

Progress heavily driven by consumer electronics

24

SLIDE 25

AMPLEX (1988) ‐ First Large Scale AMPLEX (1988) ‐ First Large Scale

Particle ph sics ASIC Particle ph sics ASIC Particle physics ASIC 16 channels, ~800 MOSFETs (~50/ch) 3µm CMOS 5V 1 1 mW/ch 16 mm² Particle physics ASIC 16 channels, ~800 MOSFETs (~50/ch) 3µm CMOS 5V 1 1 mW/ch 16 mm² 3µm CMOS, 5V, 1.1 mW/ch, 16 mm amplifier/filter/track & hold/mux for Silicon micro‐strips at UA2 3µm CMOS, 5V, 1.1 mW/ch, 16 mm amplifier/filter/track & hold/mux for Silicon micro‐strips at UA2 for Silicon micro strips at UA2 for Silicon micro strips at UA2

25

SLIDE 26

Institute WG1 Radiation WG2 Top level WG3 Sim./Ver WG4 I/O WG5 Analog WG6 IPs

FE‐I5 (2016‐17) FE‐I5 (2016‐17)

Particle physics ASIC Particle physics ASIC

Radiation Top level Sim./Ver I/O Analog IPs

Bari C A A Bergamo-Pavia A C A B Bonn C A A B B A CERN B(*) (*) A C(*) A B(*) CPPM A B C C B A Fermilab A B A LBNL B A B B A A

Particle physics ASIC 260k pixels, 1G MOSFETs (~4,000/px) 65nm 1 2V 0 5‐1 W/cm² >400mm² Particle physics ASIC 260k pixels, 1G MOSFETs (~4,000/px) 65nm 1 2V 0 5‐1 W/cm² >400mm²

19 institutions specialized working groups 19 institutions specialized working groups

LPNHE Paris A B A A NIKHEF A A A New Mexico A Padova A A Perugia B A B Pisa B A A A PSI B A C A A RAL B B A C

65nm, 1.2V, 0.5 1 W/cm , >400mm high complexity/functionality, DSP for ATLAS vertex hybrid pixels 65nm, 1.2V, 0.5 1 W/cm , >400mm high complexity/functionality, DSP for ATLAS vertex hybrid pixels

p g g p 100 collaborators (~50 ASIC designers) p g g p 100 collaborators (~50 ASIC designers)

T

rino

C B C B A A UCSC C B C A

y p y p 2X2 pixel unit 2X2 pixel unit

ARCHITECTURE ARCHITECTURE

2X2 pixel unit 2X2 pixel unit

26

SLIDE 27

Compare to Evolution of Microelectronics Compare to Evolution of Microelectronics

10µ

Xbox One 5V L 10 µm 12V first MOSFET

10G 100G 1µ 10µ

6-core I7

FE-I5

3µm 5V 800nm L 1.2µm 5V

ength L

250nm

100M 1G

rs / die

100n VMM

hannel le

130nm m 25

1M 10M

ransistor

10n

sistor ch

13 65nm 45nm 32nm 28nm

10k 100k 1M

mber of tr

1n FILAS AMPLEX

first IC

Trans

1k 10k

Num

1960 1970 1980 1990 2000 2010 2020 2030 2040

Year

100

Front‐end ASICs keep pace, but with ~decade delay

27

SLIDE 28

80

Front‐end ASICs / Year (Particle Physics) Front‐end ASICs / Year (Particle Physics)

80

f f S C f

2013 ~ 60 FE (out of ~140)

60

gns

Number of front-end ASICs for PP running and in design

~ 35 FE in design

40 r of desig 20 Number 1980 1990 2000 2010 2020 Year

arXiv:1307.3241

Exponential increase in demand for FE ASICs

28

SLIDE 29

Advances in radiation detectors are tightly

Paradigm Paradigm

Advances in radiation detectors are tightly coupled to advances in front‐end ASICs

Demand Demand Complexity

FE ASICs

Complexity Technology

FE ASICs

Design resources must be increased
Collaborations must be promoted

29

SLIDE 30

Impact of R&D on Front‐End ASICs at BNL Impact of R&D on Front‐End ASICs at BNL

Year Novel Circuit Collaborator Patent Publications Impact areas 1998 adaptive reset eV Products * * RHIC ATLAS NSLS Nonproliferation Security Medical 1998 adaptive reset eV Products



RHIC, ATLAS, NSLS, Nonproliferation, Security, Medical 1998 high order complex shaper eV Products * ATLAS, LBNE, LEGS, SANS, NSLS, Nonproliferation, Security, Medical 1999 band‐gap references R&D ATLAS, LBNE, LEGS, SANS, NSLS, Nonproliferation, Security, Medical 2001 multi‐phase peak detector R&D * * ATLAS upgrades, LEGS, SANS, NSLS, Nonproliferation, Security, Medical 2003 l i lk i d LEGS TPC * ATLAS d LEGS NSLS N lif i S i M di l 2003 low time‐walk time detector LEGS TPC * ATLAS upgrades, LEGS, NSLS, Nonproliferation, Security, Medical 2003 neighboring logic LEGS TPC * ATLAS upgrades, LEGS 2004 peak‐detector derandomizer eV Products * * NSLS, Nonproliferation 2004 low voltage adaptive reset LEGS TPC * * ATLAS upgrades, LEGS, SANS, NSLS, Nonproliferation, Security, Medical 2005 coplanar grid time correction LANL * * Nonproliferation 2006 coplanar grid ampl. correction R&D * * Nonproliferation 2006 multi‐window photon counting eV Products * * NSLS, Medical 2006 current‐mode ADC He3 SANS * * SANS, ATLAS upgrades 2006 current mode ADC He SANS SANS, ATLAS upgrades 2007 sub 10‐electron front‐end NASA * NSLS 2008 bipolar cathode timing DoD * * Nonproliferation 2010 threshold‐peak pile‐up rejector NASA * * NSLS 2011 delayed dissipative feedback ATLAS * * ATLAS upgrades NSLS Nonproliferation 2011 delayed dissipative feedback ATLAS * * ATLAS upgrades, NSLS, Nonproliferation 2011 multiphase current‐mode ADC LBNE * * LBNE, ATLAS upgrades 2012 sub‐hysteresis discrimination ATLAS * * ATLAS upgrades 2013 current‐output peak detector ATLAS * * ATLAS upgrades 2016 low‐noise termination ATLAS * ATLAS upgrades R&D 2011‐ cryogenic circuits R&D, Physics * LBNE, Neutrinoless, Dark matter, Nonproliferation, NSLS II 2011‐ flip‐chip interconnects R&D NSLSII, Nonproliferation, Neutrinoless

30

2013‐ 2D front‐ends R&D, NSLS * NSLSII, Nonproliferation, Physics 2013‐ ADCs for front‐ends R&D, SBU, LDRD? all areas 2014‐ Integrated DSP & SOC R&D, SBU all areas

 commercialization

SLIDE 31

LAr Calorimeter P2 Upgrade LAr Calorimeter P2 Upgrade

Capacitance up to 2.5nF
Termination 25/50 
Current up to 10mA
Current up to 10mA
ENI 60nA rms
Linearity 0.2%

ATLAS LAr Calorimeter y

180k channels

ns 20 @ nA 110 R kT 4 ENI

2 / 1 R

  

Can we use a termination resistor?

R P  

is

Zs Z0 = 50 Ω transmission amplifier 50 Ω

SnR

31

line amplifier

SLIDE 32

LAr Calorimeter Reference Design LAr Calorimeter Reference Design

Newcomer Rescia Newcomer‐Rescia

∙ TWEPP 2009

https://inspirehep.net/record/1196637 /files/ATL‐LARG‐PROC‐2009‐017 pdf

32

ENI 73nA @ 1nF

/files/ATL LARG PROC 2009 017.pdf

SLIDE 33

HLC ‐ Fully‐Differential FE with Passive Feedback R

‐

vo vi = ‐vo/N +

vn

+ ‐ ‐vo

inR

ii ‐vo/N

C

Input impedance Rin = R/(N+1)

C∙(N‐1)

Resistor noise 4kT/R << 4kT/Rin
Very stable termination (R, N indep. of signal current and active components)
Fully‐differential output
High linearity, ENI<60nA
G. De Geronimo

33

SLIDE 34

Conclusions Conclusions

Advances in radiation detectors are tightly coupled to

advances in front‐end ASICs

Advances in radiation detectors are tightly coupled to

advances in front‐end ASICs

Successful ASIC design needs close collaboration with

lead scientists and detector experts

Successful ASIC design needs close collaboration with

lead scientists and detector experts lead scientists and detector experts

Increase in demand, complexity and functionality

lead scientists and detector experts

Increase in demand, complexity and functionality

(towards front‐end systems‐on‐chip)

Maintaining front‐end ASIC design capability requires

(towards front‐end systems‐on‐chip)

Maintaining front‐end ASIC design capability requires

Maintaining front end ASIC design capability requires substantial increase in resources Maintaining front end ASIC design capability requires substantial increase in resources

Brookhaven National Laboratory and the ATLAS Collaboration

Acknowledgment Acknowledgment

Brookhaven National Laboratory and the ATLAS Collaboration Kai Vetter (LBL)

34