Microelectronics l for Radiation Detectors Gianluigi De Geronimo - PowerPoint PPT Presentation

Electrical and Computer Engineering Microelectronics l for Radiation Detectors Gianluigi De Geronimo gianluigi.degeronimo@stonybrook.edu, degeronimo@ieee.org Lawrence Berkeley National Laboratory December 20 th , 2016

Outline Outline • Introduction • Introduction • Charge Amplification in CMOS • Charge Amplification in CMOS • Evolution of FE ASICs • Evolution of FE ASICs • Conclusions • Conclusions 2

Sources of Electronic Noise Sources of Electronic Noise reset reset El Electronic noise: i i C F from components directly connected to input node connected to input node S v v(t) K(f,τ) C S C G S i Q∙δ(t) overall transfer function 1 1            H H f f , K K f f ,  j 2 fC F need minimum 2 poles!          2    2 2 2 S H ( f , ) df S C C H ( f ) df i v S G  2 0 0 ENC   2 h t max Time‐variant → �me‐domain analysis (noise weighting function) 3

Noise from Input Transistor Noise from Input Transistor -14 10 A A C G intrinsic gate capacitance S v [V²/Hz]   -15 10 f w S proportional to the gate size p p g v C C f f g g 1/f 1/f ectral density -16 G m 10 -17 C G = C S (capacitive matching) 10 S ( p g) G Noise spe white hi -18 10 -19 10 1 2 3 4 5 6 7 10 10 10 10 10 10 10 Frequency f [Hz]       2 2 C C a A C C From input   2 S G w w S G ENC a A transistor:   v f f C C g g C C C C G G m G G G G ASIC: power constraints S C i ƒ Tmax (max current) ƒ T 4

Input Transistor in CMOS Input Transistor in CMOS     Fix power = fix Fix power fix  2 2 F From transistor's i ' a A A C C C C  2 w w S G ENC drain current I D   white noise:  vw g I C C → size (W,L) ? → ( , ) m D G G V GS >> V th (strong inversion) V GS << V th (weak inversion) load I   2 µc W C I       D g I I ox G D g I I m D D m D D 2 nV n L L T ↓ ↓        2  L C C 2 C C V GS   2 S G   ENC ENC 2 GS S S G G ENC ENC vw vw I C I D G D • independent of L independent of L • • minimum L minimum L • C G = 0 pushes back towards • C G = C S /3 strong inversion → V GS ≈ V th (moderate inversion): model? 5

Moderate Inversion Moderate Inversion g m [mS] IC 1 IC=1 weak k moderate d strong I D [mA]    L I I 1 4 IC 1   IC  D  D g I From EKV model 2 W 2 nV µc   m D T ox nV nV T 2 2 IC IC inversion coefficient alternative: extract from simulators (BSIM) De Geronimo, I EEE TNS 52, 2005 6

Gate Capacitance Gate Capacitance C [pF] C G [pF] 2Wc ov +2/3c ox WL 2 p‐MOS p‐MOS n‐MOS n‐MOS c ox WL  C ox WL IC=1 1 overlap channel h l bulk I D [mA] 0  3   10 10 0 01 0.01 0 1 0.1 1 1 10 10 100 100    n 1       2 / 3             3 1 1 4 IC 1 C I 2 c W C WL ( IC ) 1 ( IC )      ( IC )     G D ov ox C C     C 2 n n   2 2 3 3 IC IC   Both g and C G push towards using n‐channel and L = L Both g m and C G push towards using n channel and L = L min i De Geronimo, I EEE TNS 52, 2005 7

Low‐Frequency Noise Low‐Frequency Noise -14 14 10 10 A A A A      /Hz] f w S f w S S -15 10 10 v v  v sity S v [V²/ C f g C f g G m G m -16 10 ectral dens n‐MOS -17 10 Noise spe -18 10 p‐MOS -19 10 2 3 4 5 6 7 10 10 10 10 10 10 Frequency f [Hz]          2 C   2 A C C depends depends C C C From transistor s From transistor's   2 2  2 2 f f S S G G ENC ENC a ( ( ) ) S S G G ENC a A low‐freq. noise:    vf vf f f f on τ 1 C C G G 8

Low‐Frequency Noise vs L Low‐Frequency Noise vs L 100 ] nt A feq [a.u. CMOS 180nm, IC=1 n-MOS se coefficie 0.3 at 10   3xL min A L A     f w S S quency nois  v C f g p-MOS 0.6 at G m 1 2xL min Low freq 1/f 1/f equivalent, I EEE TNS 58, 2011 i l t I TNS 58 2011 0.1 180 180 270 270 360 360 450 450 540 540 Channel length [nm]          2 2 A L C C From transistor's   2 f S G ENC a ( )    vf f low‐freq. noise: 1 C G LF noise pushes towards p‐channel & L > L min 9

Discharge Network (Reset) Discharge Network (Reset) R F R F reset • dc stabilization • discharge of C • discharge of C F C C F S S v v(t) ‐∞ K(f,τ) S i C S C A Q∙δ(t) 4 kT   2 ENC a iR iR i i R R F F F 4 4 kT kT  R I (~ 50 mV ) 4 kT "50mV rule"  F S 2 qI 2 q S R F CZT: I S = 1nA → R F >> 50 MΩ sensor shot noise examples Si: I S = 1pA → R F >> 50 GΩ from leakage current I S 10

Reset in CMOS Reset in CMOS • linear region saturation • linear region ? V G • noise self‐adjusts to I S j R F ? R F ? M F M F S   4 kTg V V  m GS TH  S I S   i M S C F C 2 2 qI qI V V V V   F F S GS TH S S v I S v(t) ‐∞ K(f,τ) C S C A S i Q∙δ(t) g q      1 m at V V 40 V GS TH I I kT kT S use large L, small W to push M F towards strong inversion Noise at discharge ? 11

Reset in CMOS ‐ Discharge Noise Reset in CMOS ‐ Discharge Noise V G Q/C Q/C M F noise increases M F at discharge C F C F τ S v ‐∞ ‐∞ τ d t C S C A S i Q∙δ(t)  a     2 2 use large τ /τ use large τ d /τ i i ENC ENC 2 2 qQ Q  id 2 d De Geronimo, NIM A 421, 1999 V a At high rate  At high rate        2 i ENC idr ENC 2 2 qQ qQ 2 τ d decreases t t alternative: use M F as switch or adopt time‐variant discharge 12

Reset in CMOS ‐ Pole Linearity Reset in CMOS ‐ Pole Linearity V G V M F M F C F ‐∞ ∞ t Q∙δ(t) C S +C A τ d τ d depends on amplitude and may affect baseline y H How to realize a linear pole‐zero cancellation ? t li li l ll ti ? 13

Reset in CMOS ‐ Pole‐Zero Cancellation Reset in CMOS ‐ Pole‐Zero Cancellation non‐linear 1 st stage of filter linear V G G R S R S M F V G G N × M N × M F C F C C S N × C F N C F Q∙δ(t) Q∙δ(t) ‐∞ ‐∞ ~N × Q∙δ(t) C S +C A 4 kT  filter noise contribution: te o se co t but o S S i i R R 2 2 R N S S Effective linear "charge amplification" by N De Geronimo, I EEE TNS 47, 2000 14

Delayed Dissipative Feedback (DDF) delay feedback of dissipative element (i.e. resistor R S ) Q∙N C S R S C F C S V 1 Q∙N C F ∙N C N V out ‐∞ ‐∞ other poles Q Q DDF shaper shaper charge gain N Q max Q max DR a DR a ≈ high analog dynamic range g g y g a ENC +ENC ENC +ENC ENC ca +ENC sh ENC ca +ENC sh De Geronimo, I EEE TNS 58, 2011 15

Front‐End ASIC for X‐Ray Spectrometers Front‐End ASIC for X‐Ray Spectrometers 6 10 10 55 Fe, T = -44 C Mn K  FWHM = 145 eV (~10e - ) Peaktime 1 µs Rate 1 kcps 6 10 50 Msamples 50 Msamples Rate = 200 kcps 55 Fe, T = -44 C Ch. 14 Mn K  4 Peaktime = 1 µs FWHM = 180 eV 10 5 10 50 Msamples   W M H V F 1 0 0 e Ch. 9 Ch. 9 d r s i Count 4 10 nts 2 FWHM = 1 7 FWHM FWHM 2 = 1.7 FWHM 10 10 Coun 3 10 no PUR (efficiency ~ 0.6) no PUR 2 10 PUR 0 10 1 PUR 10 0 1 2 3 4 5 6 7 8 9 Energy [keV] 0 10 ASIC for x‐ray spectroscopy 0 3 6 9 12 15 18 ASIC functions charge amplifier charge amplifier, Energy [keV] Energy [keV] 16 ch 2 1x4 6mm² 1mW/ch 16 ch., 2.1x4.6mm², 1mW/ch. shaper, discriminator, peak detector, Collaboration with NASA pile‐up rejector, amplitude/address multiplexer De Geronimo, I EEE TNS 57, 2010

Circuits in a Front‐End ASIC Circuits in a Front‐End ASIC • Low‐noise, low‐power charge amplifiers • gas, liquid, solid state detectors • capacitances from ~ fF to ~ nF • Switched and continuous adaptive reset • High‐order filters , stabilizers, drivers • peak time / gain adjustment • Single‐ and multi‐level discriminators g • Peak and time detectors, derandomizers • Analog memories and multiplexers • Digital memories and counters • Digital memories and counters • Configuration registers • ESD protections • Calibration pulse generators C lib i l 64‐ch. VMM ASIC • Analog‐to‐digital converters ATLAS Muon Upgrade • Digital‐to‐analog converters 14x8.5 mm², ~0.4W/cm² , / • Precision band‐gap references > 6M MOSFETs (> 90k/ch.), 2016 • Temperature sensors • Readout control logic Pace of FE ASIC Evolution? • Digital signal processing ( DSP ) • Low‐voltage differential signaling (LVSD, SLVS)