Madison SLHC Worksop HCAL SLHC DAQ E. Hazen, S. X. Wu, J. Rohlf, - - PowerPoint PPT Presentation

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Madison SLHC Worksop HCAL SLHC DAQ E. Hazen, S. X. Wu, J. Rohlf, Boston University with J. Mans, University of Minnesota A. Baden, R. Bard, University of Maryland and hopefully many others! Eric Hazen Boston University 29 November 2007

SLIDE 1

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 1

Madison SLHC Worksop HCAL SLHC DAQ

E. Hazen, S. X. Wu, J. Rohlf,

Boston University with

J. Mans, University of Minnesota
A. Baden, R. Bard, University of Maryland

and hopefully many others!

SLIDE 2

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 2

Introduction

Propose to Develop a test-bed system for

SLHC calo trigger/DAQ development

Based on uTCA standard(s)

– Input from existing HCAL (and ECAL?) front-ends – Input from existing TTC system – Output to existing GCT – Output to existing DAQ (via FRLs)

Three modules:

– Trigger/Readout Module (use GCT processor?) – Clock/Timing Module (new) – DAQ/Hub Module (new)

SLIDE 3

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 3

uTCA Standard (based on AMC)

Emphasis on high-speed communication and reliability Should be inexpensive hardware due to anticipated high telecoms volume 150mm width “shelf” Double-high double-wide module Double-high single-wide module Backplane with 21 lanes (serial) each ~ 4Gb/sec (topology not specified)

SLIDE 4

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 4

Schroff development system, about US$5k

SLIDE 5

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 5

Proposed size for our modules

SLIDE 6

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 6

Typical Crate Layout

Power MCH AMC 1 AMC 2 AMC 3 Power MCH (opt)

Up to 12 generic module (AMC) slots Power distribution MCH (Hub card) provides utility control functions Ethernet to each AMC slot for control Typical commercial backplanes provide 1 or more star connections to MCH slots, and various point-to-point connections between AMC slots

SLIDE 7

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 7

Why AMC / uTCA?

High performance (20 x 4Gb/s per slot)
Flexible (can define own backplane topology)
Inexpensive (widespread telecoms use)
Compact
It may not be the final answer for SLHC

hardware, but it is much better than VME!

SLIDE 8

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 8

Trigger/Readout Module

Use GCT processor module if possible

– Brief summary here... details later (Matt Stettler) – AMC double module – 12 in/ 12 out fibers – All 21 fabric lanes

to crosspoint sw

– Ethernet control – V5LX110T FPGA

SLIDE 9

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 9

Trigger/Readout Module

HCAL HTR Functions

– Receive front-end data – Make TP, synchronize to correct Bx – Perform RCT functions (or subset?) – Send fragments to DAQ on L1A

ECAL integration? Still too early to say, but it

would be desirable

SLIDE 10

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 10

Trigger/Readout Hardware

Virtex-5 FPGA 16 Fibers in 48 HCAL ch 16 Fibers out to GCT 72x72 Crosspoint Switch uTCA 21 3.2Gb Links 16 16 16 16 20 20 Ethernet uC Hardware maps nicely to function of one HCAL HTR 16 fibers in, 16 fibers out ~2X FPGA resources plus 10X RAM, DSPs

SLIDE 11

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 11

DAQ/Hub Module

MCH Functions of uTCA

– Power Module Management – Ethernet Switch – Carrier Management – Simple switch fabric (crosspoint switch?)

DAQ Functions

– Receive L1A and event fragments – Build events and send to FRL via SLink64

SLIDE 12

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 12

HCAL DCC limitations

HTR Inputs: 80MBytes/sec per 24 FE chan. Total of 12 used per DCC (LVDS serial) PCI bus bottleneck 2 x 100MBytes/sec max! SLINK out 256 MBytes/sec

SLIDE 13

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 13

DAQ/Hub Module

FPGA SLink 64 FED 1 SLink 64 FED 2 ? Crosspoint Switch uTCA 3.2Gb Links Ethernet Switch uC CPLD/FPGA Management Functions Other DAQ Output options i.e. 10-40GbE SDRAM

SLIDE 14

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 14

DAQ/Hub Module

Plenty of BW – 3.2Gb/sec per port ~ 400MB/s
Much simpler architecture with all in one FPGA.
Bottleneck is now DAQ output... if DAQ is

upgraded we need to explore higher-bandwidth

ptions.

SLIDE 15

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 15

uTCA Prototype System

Power DAQ/MCH T/R AMC T/R AMC T/R AMC T/R AMC T/R AMC T/R AMC Power Timing/Control T/R AMC T/R AMC T/R AMC T/R AMC T/R AMC T/R AMC Up to 16x12 Fibers in (576 HCAL channels, same as current crate) S-Link 64 (1 or 2) TTC Fiber Up to 16x12 Fibers out to GCT Ethernet (control) Modules will be compatible with commercial backplane

r custom backplane developed for GCT

Start with minimal system (one of each module) this year

SLIDE 16

29 November 2007 Eric Hazen – Boston University SLHC Calo Trigger Workshop - Madison 16

Development Plan

Procure and Study Standards (AMC, uTCA etc)

– Have standards... reading them now :)

Buy development hardware

– crate, power, backplane

Develop DAQ/Hub and Trigger/Control modules
Obtain a processor module when available
Commission and test with simple firmware
Hopefully by Summer '08!