System Integration Issues System Integration Issues of DC to DC - - PowerPoint PPT Presentation

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System Integration Issues System Integration Issues of DC to DC - - PowerPoint PPT Presentation

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System Integration Issues System Integration Issues of DC to DC converters in of DC to DC converters in the sLHC Trackers the sLHC Trackers the sLHC Trackers the sLHC Trackers B. Allongue a , G. Blanchot a , F. Faccio a , C. Fuentes a,b , S.

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SLIDE 1

System Integration Issues System Integration Issues

  • f DC to DC converters in
  • f DC to DC converters in

the sLHC Trackers the sLHC Trackers the sLHC Trackers the sLHC Trackers

  • B. Allonguea, G. Blanchota, F. Faccioa, C. Fuentesa,b, S. Michelisa,c, S. Orlandia

a CERN, 1211 Geneva 23, Switzerland b UTFSM, Valparaiso, Chile c EPFL, Lausanne, Switzerland

georges.blanchot@cern.ch TWEPP 2009, Paris

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SLIDE 2

Outline Outline

  • DC/DC Converters for Trackers at sLHC.

DC/DC Converters for Trackers at sLHC.

  • System integration issues to be considered.

System integration issues to be considered.

  • Radiated couplings and inductor.

Radiated couplings and inductor.

  • Conducted noise and layout.

Conducted noise and layout.

  • Conducted noise and layout.

Conducted noise and layout.

  • Susceptibility of the

Susceptibility of the ABCn ABCn hybrids prototypes. hybrids prototypes.

  • Conclusions

Conclusions

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SLIDE 3

DC/DC Converters at sLHC DC/DC Converters at sLHC

Requirements:

To deliver increased amount of power. To contain or even reduce thermal losses. To minimize the material needed to bring the power in.

  • Cables
  • Boards

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  • Boards

To be compatible with the environment

  • Radiation,
  • Magnetic field
  • Space
  • Not to inject noise in the system.

A powering scheme based on DC/DC converters that fulfill

these requirements is proposed.

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SLIDE 4

Powering Scheme at sLHC Powering Scheme at sLHC

Building Blocks Building Blocks 10-12V Distribution based on 2 conversion stages Distribution based on 2 conversion stages Example design shown for ATLAS short strip concept

stave stave

Optical link

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Stage1:

  • Inductor-based buck
  • Vin = 10-12 V
  • Vout = 2.5-1.8 V
  • Pout = 2-4 W

Stage2:

  • On-chip switched capacitor
  • Vin = 2.5-1.8 V
  • Conversion ratio ½ or 2/3
  • Iout = 20-100 mA

Same blocks can be combined differently to meet custom system requirements

10-12V 2.5 V

GBT,Opto Stave Controller 1.25V

10-12V

Detector

Intermediate voltage bus

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SLIDE 5

System Integration Issues System Integration Issues

10-12V

Detector

Intermediate

To which noise sources is the system sensitive and how much ? What are the noise sources

  • f the converter and how to

quantify them ?

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10-12V

Intermediate voltage bus

What is the best layout ? The proposed scheme requires to have the converter very close to the detector and ASICs. The DC/DC noise must be minimized. The immunity of the system against couplings must be maximized. What is the best inductor ?

ASIC DC/DC IN Filter

π π π π

OUT Filter

π π π π

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SLIDE 6

Outline Outline

  • DC/DC Converters for Trackers at sLHC.

DC/DC Converters for Trackers at sLHC.

  • System integration issues to be considered.

System integration issues to be considered.

  • Radiated couplings and inductor.

Radiated couplings and inductor.

  • Conducted noise and layout.

Conducted noise and layout.

  • Conducted noise and layout.

Conducted noise and layout.

  • Susceptibility of the

Susceptibility of the ABCn ABCn hybrids prototypes. hybrids prototypes.

  • Conclusions

Conclusions

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SLIDE 7

Radiated Couplings and Inductor Radiated Couplings and Inductor

A triangular current at switch frequency, whose amplitude is of few amperes, flows in the DC/DC output inductor. This results in a radiated magnetic field, whose direction and intensity will strongly depend on the inductor topology.

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7 inductor topology. Compared topologies:

  • Solenoid, 500 nH, the full magnetic field is

radiated along its axis (N loops). Shielding not possible without reducing the inductance value.

  • Air core toroid, 200 nH, main field is confined in

the toroid volume; residual field due to current along the tore axis (1 loop). Shielding possible.

  • PCB toroid, 500 nH, geometry limited by PCB
  • technology. Shielding possible in the PCB layers.
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SLIDE 8

Radiated Couplings and Inductor Radiated Couplings and Inductor

d h=10 mm

H Field measured with calibrated and amplified loop probe:

  • solenoid, air core toroid, PCB toroid.
  • shielding of coil, shielding of pins using 35 um copper foils.

Solenoid is the most noise and can’t be shielded. Air core toroid is good and shield reduces furthermore

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8 shield reduces furthermore the field. PCB toroid is very effective if shielded. It has more than 300 times less noise than the solenoid and 4 times less than the shielded air core toroid. The loop formed by the inductor pins is a non negligible source of H field: the connection pins must be shielded too.

50 dB = 315 13 dB = 4.5

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SLIDE 9

Outline Outline

  • DC/DC Converters for Trackers at sLHC.

DC/DC Converters for Trackers at sLHC.

  • System integration issues to be considered.

System integration issues to be considered.

  • Radiated couplings and inductor.

Radiated couplings and inductor.

  • Conducted noise and layout.

Conducted noise and layout.

  • Conducted noise and layout.

Conducted noise and layout.

  • Susceptibility of the

Susceptibility of the ABCn ABCn hybrids prototypes. hybrids prototypes.

  • Conclusions

Conclusions

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SLIDE 10

Conducted Noise Conducted Noise

Conducted noise is emitted in the form of currents by the converter into the cables:

  • Differential Mode Noise (ripple)
  • Common Mode Noise (in GND

plane). It is measured on a dedicated setup, that uses Line Impedance

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10 10 that uses Line Impedance Stabilization Networks to normalize the measurement. The measurement is made with calibrated current probes and on the LISN ports. The conducted noise was radically reduced on past prototypes. It was found that the layout and the placement of components is determinant to reduce the conducted noise.

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SLIDE 11

Performance of DC/DC Prototypes Performance of DC/DC Prototypes

Proto#2 reached 60 dBuA = 1mA at Fsw Proto#2 reached 50 dBuA = 320uA at 10 MHz Significant noise reduction in Proto#3 Proto#5 reaches 25 dBuA = 17uA at Fsw, and 10 dBuA = 3uA at 10 MHz: the emission of CM current has been reduced by an order of more than 50 at switch frequency, and by two orders of magnitude at 10 Mhz. Low Noise was also achieved with the AMIS2 ASIC Prototype

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SLIDE 12

AMIS2 Tests: Layout AMIS2 Tests: Layout

AMIS2 V1 AMIS2 V3

In/Out on opposite sides Filters on opposite sides In/Out on corner sides Filters close together

ASIC DC/DC IN Filter

π π π π

OUT Filter

π π π π

Filters on opposite sides Filters close together

Several layouts have been tried for the same schematic using the AMIS2 ASIC. Comparison of two of those are shown here: Separated input and output (and filters). Input and Output close together. Different positions and types of the coils were tried.

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SLIDE 13

AMIS2 Tests: Layout Issues AMIS2 Tests: Layout Issues

AMIS2 V1 AMIS2 V3 CM DM

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SLIDE 14

AMIS2 Tests: Layout Issues AMIS2 Tests: Layout Issues

AMIS2 V1 AMIS2 V3 In/Out Separation: Large distance between In/Out GND pins: In/Out Close Together: Small distance between In/Out GND pins: Large distance between In/Out GND pins:

  • Vcm = Lgnd*(dI/dt) develops between

the pins and leads to worse CM noise. But the distance between In/Out filter reduces couplings between filter inductors:

  • Good attenuation of ripple.

Easier to fit big coils on top side. The performance could not be improved with different placements: the layout dominates noise performance. Small distance between In/Out GND pins:

  • Lgnd is much smaller, therefore CM is

reduced (10 dB to 15 dB). Proximity of In/Out filter and L inductors couples DM currents between In and Out.

  • Slightly worse DM attenuation.

Difficult to fit big coils on top.

  • Stacked coils will couple.

Room for improvements with different coil arrangements (see next).

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SLIDE 15

AMIS2 Tests: Coil Top/ AMIS2 Tests: Coil Top/Bot Bot

AMIS2 V3, TOP The placement of the coil has a negligible impact

  • n V1 because the main inductor is at some

distance of the pi filters, therefore there is not an important coupling. This is not the case for V3, which has its noise dominated by couplings from the main coil. CM AMIS2 V3 BOT DM

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SLIDE 16

AMIS2 Tests: Inductor Type AMIS2 Tests: Inductor Type

CM AMIS2 V3 DM

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SLIDE 17

AMIS2 Tests: Inductor Type AMIS2 Tests: Inductor Type

AMIS2 V3 PCB Inductor on top: CM performance of AMIS2 V3 is Solenoid Inductor on top: The CM looks very slightly better (few superior to V1 because of its layout. The PCB coil is very large for V3 board: it falls above the filter coils, which limits still the DM performance.

  • Higher switching frequencies would

allow reducing its size and reduce therefore the couplings It must be reminded that the shielded PCB coil radiates much less H field than its solenoid counterpart. dB) at high frequencies. The coil is smaller and fits better above the ASIC: it is away of the filter coils which explains the better DM. The coil was oriented such that the main field stays away of the connectors and filters.

  • But the main field is fully radiated

towards the hybrid and detector.

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SLIDE 18

Outline Outline

  • DC/DC Converters for Trackers at sLHC.

DC/DC Converters for Trackers at sLHC.

  • System integration issues to be considered.

System integration issues to be considered.

  • Radiated couplings and inductor.

Radiated couplings and inductor.

  • Conducted noise and layout.

Conducted noise and layout.

  • Conducted noise and layout.

Conducted noise and layout.

  • Susceptibility of the

Susceptibility of the ABCn ABCn hybrids prototypes. hybrids prototypes.

  • Conclusions

Conclusions

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SLIDE 19

Tests with Tests with ABCn ABCn w/o strips w/o strips

200 250 300 350 400 450 500 550 600 10 20 30 40 50 60 70 80 90 Input Noise [ENC] @2fC µ =392.2552 σ =27.4935 LPL Hybrid Stream 0 using Linear PS 40 50 60 70 µ =392.6322 σ =26.9963 LPL Hybrid Stream 0 using DCDC

Liverpool Hybrid with linear PS and with DCDC

Two hybrid prototypes tested, 20 ABCn chips on each, 4A DC, without strips detector mounted:

  • Liverpool Hybrid, requires one DCDC or linear PS.
  • KEK Hybrids, requires two DCDC or linear PS.
  • Noise estimation: Qe*(RMS of fitted scurves)/Gain [ENC].

No noise degradation observed when using the DCDC, even when powering the analog part directly from DCDC (KEK case).

200 250 300 350 400 450 500 550 600 10 20 30 Input Noise [ENC] @2fC 200 250 300 350 400 450 500 550 600 10 20 30 40 50 60 70 80 Input Noise [ENC] @2fC µ =386.1446 σ =27.4474 KEK Hybrid Stream 0 using DCDC 200 250 300 350 400 450 500 550 600 10 20 30 40 50 60 70 80 Input Noise [ENC] @2fC µ =388.087 σ =26.4483 KEK Hybrid Stream 0 using Linear PS

KEK Hybrid with linear PS and with DCDC

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SLIDE 20

Tests with Tests with ABCn ABCn w/o strips (2) w/o strips (2)

40 50 60 70 80 µ =388.087 σ =26.4483 KEK Hybrid Stream 0 using Linear PS

Histograms are obtained from Scurve fits at 2 fC with non equalized gains. Radiated coupling test on the KEK hybrid using two DCDC converters facing the ABCn chips. No observable noise degradation when exposed to DCDC magnetic field from coils.

200 250 300 350 400 450 500 550 600 10 20 30 40 50 60 70 80 Input Noise [ENC] @2fC µ =386.41 σ =27.7643 KEK Hybrid Stream 0 with DCDC on Hybrids 200 250 300 350 400 450 500 550 600 10 20 30 Input Noise [ENC] @2fC

KEK Hybrid with linear PS and with DCDC on top

  • f ASICs

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SLIDE 21

Tests with Tests with ABCn ABCn w/o strips w/o strips

ENC at 2 fC Average RMS Row 0 Row 1 Row 0 Row 1 LPL Linear PS 392.3 390.8 27.5 27.7 LPL DC/DC 392.6 390.9 27.0 27.9 KEK Linear PS 388.1 390.0 26.4 27.6 KEK DC/DC 386.1 387.0 27.4 26.0 KEK DC/DC 386.1 387.0 27.4 26.0 KEK Edge 386.4 388.0 27.8 26.3

There has been no significant increment of noise neither due to conducted noise or to radiated couplings on the ASICs. It must be noticed that the channels were not gain equalized: the gain dispersion can hide the noise sensitivity, if there is any. It must be noted also that the KEK hybrid powers the analog part of ABCn directly from a DCDC, while the Liverpool hybrid enables the ABCn LDO regulator.

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SLIDE 22

Tests with Tests with ABCn ABCn with strips with strips

One out of two ABCn hybrids tested with the same DC/DC converters in three locations: far, close and on the strips edge. The hybrids are bonded to strips. Far Close Edge The gains are first equalized through a 3-point gains calibration run. Afterwards, Scurves are

  • btained without charge to build

up occupancy plots. The noise is estimated as the occupancy for a threshold setting

  • f about 110mV, which is equivalent to 1fC for equalized gains.

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SLIDE 23

Tests with Tests with ABCn ABCn with strips with strips

Reference Far Close Edge The occupancy expands to higher thresholds, but the effect becomes critical only if the coil is facing the strips.

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Linear PS: the Scurves fall to zero above Vth = 60 mV, and the occupancy noise is zero at 1fC equivalent. Occupancy charts are very sensitive to dead or unstable channels.

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SLIDE 24

Tests with Tests with ABCn ABCn with strips with strips

Reference Far Edge Close

Average RMS

Fitted S-Curves RMS distributions Only the channels directly exposed to the inductor field (< 2cm, row 1) are sensitive to it. The other channels are insensitive to it (row 1) even when the coil is facing the edge of the hybrid.

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ENC*G/Qe Average RMS Row 0 Row 1 Row 0 Row 1 Reference 10.2 10.1 0.41 0.32 Far 9.82 9.80 0.40 0.30 Close 9.80 9.79 0.38 0.30 Edge 10.1 12.6 0.37 2.36

Sensitive area

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SLIDE 25

Impact of the bonding pattern Impact of the bonding pattern

The bonding pattern is an alternating structure that forms a loop with the ground plane. The loop is exposed to B field from the converter and injects parasitic currents into the bondings. The current is proportionnal to the loop area, resulting in a patterned noise structure.

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SLIDE 26

Conclusions Conclusions

  • Different coil configurations were explored, looking for the minimum

Different coil configurations were explored, looking for the minimum emitted magnetic field: emitted magnetic field:

  • Solenoid discarded, Air core

Solenoid discarded, Air core toroid toroid is better. is better.

  • Shielded PCB

Shielded PCB toroid toroid brings the lowest emission, but hard to manufacture. brings the lowest emission, but hard to manufacture.

  • Compact layouts help reducing the emission of noise:

Compact layouts help reducing the emission of noise:

  • Reduced ground inductance in power path = less CM noise.

Reduced ground inductance in power path = less CM noise.

  • In and Out must sit close together.

In and Out must sit close together.

  • In and Out must sit close together.

In and Out must sit close together.

  • ASIC development favors reduction of noise emissions.

ASIC development favors reduction of noise emissions.

  • An increasing switching frequency would allow reducing L and C sizes.

An increasing switching frequency would allow reducing L and C sizes.

  • Noise susceptibility of tracking detectors is found at the signal input

Noise susceptibility of tracking detectors is found at the signal input

  • Only sensitive if strips bonded.

Only sensitive if strips bonded.

  • Bonds are only sensitive to DCDC within a radius of 2 cm approx.

Bonds are only sensitive to DCDC within a radius of 2 cm approx.

  • Shorter bonds, or alternative mounting options are the most efficient ways to

Shorter bonds, or alternative mounting options are the most efficient ways to improve the system immunity against noise. improve the system immunity against noise.

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SLIDE 27

Backup Slide Backup Slide

  • Field Lines from Coils and symmetry issues

Field Lines from Coils and symmetry issues

Optimization of shielded PCB air-core toroids for high efficiency dc-dc converters

  • S. Orlandi1, B. Allongue1, G. Blanchot1, S. Buso2, F. Faccio1, C. Fuentes1,3, M. Kayal4,
  • S. Michelis1,4, G. Spiazzi5

1 CERN

1211 Geneva 23 Switzerland

2 Dept. of Technical

Management of Industrial Systems - DTG University of Padova, Italy

3 UTFSM,

Valparaiso,

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Valparaiso, Chile

4 EPFL,

Lausanne, Switzerland

5 Dept. of Information

ECCE 2009 Conference, San Jose, CA, USA