Low Power DSP Architectures Trevor Mudge, Bredt Professor of - - PDF document

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University of Michigan – ARM June 09

Overview

• AnySP
• SODA++
• Increase the Application Domain of the Wireless

baseband architecture

• Diet-SODA
• SODA- -
• Taking the sugar out of SODA

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Low Power DSP Architectures

Trevor Mudge, Bredt Professor of Engineering, The University of Michigan, Ann Arbor 1st tubs.CITY Symposium

July 1 – 3, 2009, Braunschweig

Mark Woh1, Sangwon Seo1, Ron Dreslinski, Geoff Blake, Scott Mahlke1, Chaitali Chakrabarti2, Krisztian Flautner3 University of Michigan – ACAL1 Arizona State University2 ARM, Ltd.3

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The Old Mobile Phone The Modern Mobile Phone

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Video Recording Video Editing Higher Data Rates

Photos From - http://www.engadget.com/2009/06/10/iphone-3g-s-supports-opengl-es-2-0-but-3g-only-supports-1-1/ http://www.apple.com/iphone

3D Rendering Advanced Image Processing

• Future phones are becoming more complex
• Richer applications require much more

requirements

• How do phones handle this now?

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Inside Today’s Smart Phones

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Inside the OMAP3430 Application Processor

Inside the X-Gold 608 (Representation of QCOM)

• Modern phones are looking like Frankenchips!
• Some cores unused and functionality duplicated

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Cost for Multi-System Support

• Supporting multiple systems is reserved for the most expensive phones
• Cost is in supporting all the systems that may or may not be used at once

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Data gathered from

• Ramacher, U. 2007. Software-Defined Radio Prospects for Multistandard Mobile Phones. Computer 40, 10 (Oct. 2007)
• Finchelstein, D.F.; Sze, V.; Sinangil, M.E.; Koken, Y.; Chandrakasan, A.P., "A low-power 0.7-V H.264 720p video decoder,"

Solid-State Circuits Conference, 2008. A-SSCC '08.

Programmable Unified Architectures Provide  Lower Cost  Faster Time to Market  Support for Multiple Applications (Current and Future)  Bug Fixes After Manufacturing So where do we start?

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View of the Unified Architecture World

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3G ISP

V i d e

• WiFi

GSM

2D/3D

3G ISP

V i d e

• WiFi

GSM

2D/3D

GSM ISP WiFi 3G 2D/3D V i d e

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Power/Performance Requirements for Multiple Systems

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Different applications have different power/performance characteristics! We need to design keeping each application in mind! (Not GPP but Domain Specific Processor)

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The Applications

Is there anything we can learn from the applications themselves?

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H.264 Basics

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T.-A. Liu, T.-M. Lin, S. -Z. Wang, et al. “A low-power dual-mode video decoder for mobile applications,” IEEE Communications Magazine, volume 44, issue 8, pp.119-126, Aug. 2006. 10 10 10

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4G Wireless Basics

• Three kernels make up the majority of the

work

• FFT – Extract Data from Signals
• STBC – Combine Data into More Reliable Stream
• LDPC – Error Correction on Data Stream

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Mobile Signal Processing Algorithm Characteristics

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• Algorithms have different SIMD widths
• From very large to very small
• Though SIMD width varies all algorithms can exploit it
• Large percentage of work can be SIMDized
• Larger SIMD width tend to have less TLP

Algorithm
 SIMD
 Scalar
 Overhead
 SIMD
Width
 Amount
 Workload
(%)
 Workload
(%)
 Workload
(%)
 (Elements)


• f
TLP


4G


FFT
 75
 5
 20
 1024
 Low
 STBC
 81
 5
 14
 4
 High
 LDPC
 49
 18
 33
 96
 Low


H.264


Deblocking
Filter
 72
 13
 15
 8
 Medium
 Intra‐PredicMon
 85
 5
 10
 16
 Medium
 Inverse
Transform
 80
 5
 15
 8
 High
 MoMon
CompensaMon
 75
 5
 10
 8
 High


SIMD comes at a cost!

• Register File Power
• Data Movement/Alignment Cost

SIMD architectures have to deal with this!

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Traditional SIMD Power Breakdown

• Register File Power consumes a lot of power in traditional

32-wide SIMD architecture

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Register File Access

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• Many of the register file access do not have to go back to the

main register file

0%
 10%
 20%
 30%
 40%
 50%
 60%
 70%
 80%
 90%
 100%


FFT
 STBC
 LDPC
 Deblocking
 Filter
 Intra‐PredicMon
 Inverse
 Transform


Register
Access
 Bypass
Read
 Bypass
Write


Lots of power wasted on unneeded register file access!

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Instruction Pair Frequency

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Like the Multiply-Accumulate (MAC) instruction there is opportunity to fuse other instructions A few instruction pairs (3-5) make up the majority of all instruction pairs!

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Data Alignment Problem!

• H.264 Intra-prediction has 9 different prediction modes
• Each prediction mode requires a specific permutation

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Traditional SIMD machines take too long or cost too much to do this Good news – small fixed number patterns per kernel Intra‐PredicMon


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More Data Alignment Problems!

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Adder tree can accelerate not only matrix operations! Many different video kernels can be accelerated too! Inverse
Transform


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Even More Data Alignment!

• Techniques like 2D-Wave and 3D-Wave decoding for H.264

helps increase amount of parallelism but we have to be able to access different macroblocks for each parallel computation

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C.H. Meenderinck, A. Azevedo, B.H.H. Juurlink, M. Alvarez, A. Ramirez, Parallel Scalability of Video Decoders, Journal of Signal Processing Systems, August 2008

Block based decoding requires us to access different locations of memory for each task We cannot just rely of fetching contiguous sets of data

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Summary

• Conclusion about 4G and H.264
• Lots of different sized parallelism
• From 4 wide to 96 wide to 1024 wide SIMD
• Which means many different SIMD widths need to be supported
• Very short lived values
• Lots of potential for instruction fusings
• Limited set of shuffle patterns required for each kernel

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AnySP Design

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SODA SIMD Architecture

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32-Wide SIMD with Simple Shuffle Network

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AnySP Architecture – High Level

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8 Groups of 8-Wide Flexible Function Units 128x128 16bit Swizzle Network 16 Banked Memory with SRAM-based Crossbar Multiple Output Adder Tree Temporary Buffer and Bypass Network Datapath AGU and Scalar Pipeline

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Multi-Width Support

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Normal 64-Wide SIMD mode – all lanes share one AGU Each 8-wide SIMD Group works on different memory locations of the same 8-wide code – AGU Offsets

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AnySP FFU Datapath

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Flexible Functional Unit allows us to

• 1. Exploit Pipeline-parallelism by joining two lanes together
• 2. Handle register bypass and the temporary buffer
• 3. Join multiple pipelines to process deeper subgraphs
• 4. Fuse Instruction Pairs

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AnySP Results

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Simulation Environment

• Traditional SIMD architecture comparison
• SODA at 90nm technology
• AnySP
• Synthesized at 90nm TSMC
• Power, timing, area numbers were extracted
• Kernels were hand written and optimized
• 4G – based on a NTT DoCoMo 4G test setup
• H.264 – 4CIF@30fps

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AnySP Speedup vs SIMD-based Architecture

• For all benchmarks we perform more than 2x better

than a SIMD-based architecture

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AnySP Energy-Delay vs SIMD-based Architecture

• More importantly energy efficiency is much better!

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AnySP Power Breakdown

• We estimate that both H.264 and 4G wireless can be done

in under 1 Watt at 45nm

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Conclusion & Future Work

• Conclusion
• We have presented an example architecture that could

possibly meet the requirements of 100Mbps 4G and HD video on the same platform

• Under the power budget and meeting the performance at 45nm
• Future and Ongoing Work
• Application-specific language
• Larger class of algorithms for AnySP
• Better utilization of resources for non-parallel kernels
• Speedup sequential parts

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Diet-SODA

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Diet SODA

• SODA, Ardbeg, AnySP may be too powerful for the

application

• Simple Imaging processing for cameras
• Audio processing for voice
• Lose flexibility and generality of Ardbeg, AnySP for

performance at less # of gates

• Build a modular design which people can add SIMD

groups and special function blocks to increase performance, at cost of area but allow voltage scaling

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Histogram Equalization

• Spreads out an unevenly distributed histogram
• Increases contrast

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Histogram Equalization

for(i=0; i<length; i++) { for(j=0; j<width; j++){ k = image[i][j]; histogram[k] = histogram[k] + 1; } } for(i=0; i<length; i++){ for(j=0; j<width; j++){ k = image[i][j]; image[i][j] = sum_of_h[k] * constant; } } Hard to parallelize because of histogram[k] We can parallelize the load but we may suffer on the SIMD to scalar transfer

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Basic Edge Detection

• detect_edges : 8 directional masks ( Sobel ) + thresholding

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Basic Edge Detection

Can be easily parallelized across multiple masks or across multiple images

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for(a=-1; a<2; a++){ for(b=-1; b<2; b++){ sum = sum + image[i+a][j+b] * mask_0[a+1][b+1]; } }

for(i=0; i<rows; i++){ for(j=0; j<cols; j++){ if(out_image[i][j] > high) {

• ut_image[i][j] = new_hi;

} else {

• ut_image[i][j] = new_low;

} } }

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Basic Edge Detection

Operations are applied on 3x3 matrices 1) Reduction tree (need a function of sum of 9 values) 2) Select max function 3) Threshold operation if (out_image > threshold)

• ut_image = hi

else

• ut_image = low

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Performance Estimate

• Estimate for how many cycle we need on 2048x1536 images

3.1 Megapixel

• Unoptimized SIMDized kernels assuming 16-wide SIMD
• Most work is done on 9-wide (3x3) data elements
• Adding multiple SIMD groups can increase performance in

most kernels

SequenMal
(Mcycle)
 SIMDized
(Mcycle)
 Histogram
EqualizaMon
 75
 75
 Edge
DetecMon
 3267
 530
 Homogeneity
Edge
DetecMon
 556
 50
 Filter
 411
 81


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Modular Design Consideration

• Build a highly application specific modular core
• Depending on which application supported user can add or

remove specialized hardware

• Design requirement tradeoff
• Smallest Area
• Use minimum number of SIMD groups or run SIMD

groups faster

• Faster performance
• Add more SIMD Groups
• Lower Power
• Add more SIMD Groups and lower frequency and

lower VDD for same throughput

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The End

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