Lecture 7: Processor Storage and Control The Final Destination - PowerPoint PPT Presentation

Lecture 7: Processor Storage and Control

The Final Destination PCWriteCond Control PCSource Unit PCWrite ALUOp IorD ALUSrcB MemRead ALUSrcA MemWrite RegWrite MemtoReg RegDst IRWrite Opcode 0 1 2 Shift left 2 Instruction Registers [31-26] 0 Read reg 1 Instruction 0 A PC [25-21] Address Zero Read 1 A 1 data 1 Instruction Read reg 2 Memory [20-16] data ALU ALU result Instruction 0 Out Write [15-0] data Write reg Read B 0 1 data 2 4 1 B ALU Instruction 2 Write data Memory Register 3 0 Memory 1 data register Sign Shift left 2 extend

Deconstructing processors Controller Thing Storage Arithmetic Thing Thing

The “Storage Thing” aka: the register file and main memory

Memory and registers § The processor has registers that store a single value (program counters, instruction registers, etc.) § There are also units in the CPU that store large amounts of data for use by the CPU: ú Register file: Small number of fast memory units that allow multiple values to be read and written simultaneously. ú Main memory: Larger grid of memory cells that are used to store the main information to be processed by the CPU.

Memory and registers In terms of access speed: § Register = The plate in front of you § Cache = The fridge in the kitchen § Memory (RAM) = The corner grocery store § Hard Disk = The farm in the prairies § Network = The farm in another country

Register File Functionality Typical Setup: (MIPS) 32 registers Each register is 32 bits Read/Write Register 0 5 bit addressing Destination Reg. Register 1 (n-bit address) Register 2 Data to write … Register Fil e Value from … Register A Reg. A (n-bit address) Register 2 n Register B Value from (n-bit address) Reg. B Register File

Register File – Write Operation Load Enable Reg A select Data 2 Load R 0 0 1 A Load 2 R 1 3 Load R 2 0 1 B Load 2 R 3 3 0 1 2 3 2 Decoder Reg B select 2 Destination Reg. Address

Register File – Read Operation Load Enable Reg A select Data 2 Load R 0 0 1 A Load 2 R 1 3 Load R 2 0 1 B Load 2 R 3 3 0 1 2 3 2 Decoder Reg B select Note: Data , A and B , and all 2 the registers ( R 0 to R 3 ) have Destination the same bitwidth (e.g., n bits). Reg. Address

Main Memory and Addressing Address § Registers files are fast 0 01001010 but too costly for 1 11110000 word 2 01001010 storing lots of data. 3 11101010 § Instead store data in 4 00001110 main memory. 5 ... word 6 ... § Main memory is 7 addressed in units of 8 bytes (8-bits) 9 word 10 § Every group of 4 bytes 11 is one 32-bit word. 12

Electronic Memory § Like register files, main memory is made up of a decoder and rows of memory units. Row 0 Row 1 m Address Decoder Row 2 Lines Row 3 ... Row 2 m -1 § There are 2 m rows. ... ú m is the address width D 0 D 1 D 2 D n-1 § Each row contains n bits. Data ú n is the data-width Lines § What’s the size of this memory? ú 2 m * n bits => 2 m * n / 8 Bytes

Memory Array wordline 0 Cell 2 Cell 1 Cell 0 wordline 1 Decoder Cell 2 Cell 1 Cell 0 wordline 2 Cell 2 Cell 1 Cell 0 wordline 3 Cell 2 Cell 1 Cell 0 bitline 2 bitline 1 bitline 0

Memory Array – signals Wordline: which memory Decoder row (word) to read/write Bitline: read/write data Also add read/write signal. Can add column select line if needed.

Data Bus § Communication between components takes place through groups of shared wires called a bus (or data bus). § Multiple components can read from a bus, but only one can write to a bus at a time. ú Also called a bus driver. § Each component has a tristate buffer that feeds into the bus. When not reading or writing, the tristate buffer drives high impedance onto the bus.

Controlling the flow § Since some lines (buses) WE will now be used for both input and output, we A Y introduce a (sort of) new gate called the tri-state buffer. § When WE (write enable) WE A Y signal is low, buffer 0 X Z output is a high impedance signal. 1 0 0 ú The output is neither 1 1 1 connected to high voltage or to the ground.

Controlling the flow WE § WE = 1 ú A is connected to Y A Y § WE = 0 ú A is disconnected from Y § Used to control data lines so WE A Y that only one device can write 0 X Z onto the bus at any time 1 0 0 (Multiple devices reading 1 1 1 is usually fine)

Example: Asynchronous SRAM Interface Address Data (n-bit) (m-bit) SRAM CE Read/Write OE Chip Enable Read/Write Output Enable AccessType (CE) (OE) 0 0 1 SRAM Write 0 1 0 SRAM Read 1 X X SRAM not enabled

Asynchronous SRAM - Timing waveforms time SRAM Read SRAM Write Address __ CE Read/ Write __ OE hi-Z hi-Z hi-Z Data Data to SRAM Data from SRAM § Each memory read and write is done in stages. § Each stage takes a certain amount of time.

Reading From Memory – Timing Constraints Read Cycle Time Address t AA t OHA t OHA Data Out Prev. data valid Data valid § t AA = Address Access time ú Time needed for address to be stable before reading data values (~10ns). § t OHA = Output Hold time ú Time output data is held after change of address (~2ns).

Writing To Memory – Timing Constraints Write Cycle Time Address t SA t HA Read/ Write t AW t SD t HD Data In Valid Data-In § t SA = Addr. Setup Time (~ 0 ns) ú Time for address to be stable before enabling write signal. § t AW = Address Setup Time to Write End (~8ns) § t SD = Data Setup to Write End (~ 6 ns) ú Time for data-in value to be set-up at destination. § t HD = Data Hold from Write End (~ 0 ns) ú Time data-in value should stay unchanged after write signal changes.

Memory vs registers § Memory houses most of the data values being used by a program. § Registers are for local / temporary data stores, meant to be used to execute an instruction. ú Registers are can host memory between instructions (like scrap paper for a calculation). ú Some have special purpose or used to control execution, like the stack pointer register

Memory vs registers § In terms of access speed ú Register = The plate in front of you ú Cache = The fridge in the kitchen ú Memory (RAM) = The corner grocery store ú Hard Disk = The farm in the prairies ú Network = The farm in another country

Load-Store Architecture § The MIPS processor architecture we are building is a load-store architecture. ú We load data from main memory to registers ú Process them using ALU ú Store back in main memory § We do either ALU or memory, not both. § This simplifies design of datapath and instruction set.

§ Now we know what the Arithmetic and Storage Things do Controller Thing Storage Arithmetic Thing Thing

Break 1981 : - 2GB - 3MB/s - $140,000 2019: - 200GB - 50MB/s - $25

§ Before we get to the controller § Need to talk about the data path This part here Controller Thing Storage Arithmetic Thing Thing

Processor Datapath Diagram PCWriteCond Control PCSource Unit PCWrite ALUOp IorD ALUSrcB MemRead ALUSrcA MemWrite RegWrite MemtoReg RegDst IRWrite Opcode 0 1 2 Shift left 2 Instruction Registers [31-26] 0 Read reg 1 Instruction 0 A PC [25-21] Address Zero Read 1 A 1 data 1 Instruction Read reg 2 Memory [20-16] data ALU ALU result Instruction 0 Out Write [15-0] data Write reg Read B 0 1 data 2 4 1 B ALU Instruction 2 Write data Memory Register 3 0 Memory 1 data register Sign Shift left 2 extend

Datapath vs. Control § Datapath: where all data computations take place. ú Often a diagram version of real wired connections. § Control unit: orchestrates the actions that take place in the datapath. ú The control unit is a big finite-state machine that instructs the datapath to perform all appropriate actions.

Datapath example

Example: Calculate x 2 + 2x § Assume that you have access to a value from an external source. How would you compute x 2 + 2x with components you’ve seen so far? § Components needed: ú ALU (to add, subtract and multiply values) ú Multiplexers (to determine what the inputs should be to the ALU) ú Registers (to hold values used in the calculation)

Example schematic X LdRA LdRB RA RB 0 1 0 1 SelxA SelAB ALUop ALU

Making the calculation Steps for x 2 + 2x: § Load X into RA & RB § Multiply RA & RB ú Store result in RA § Add X to RA ú Store result in RA § Add X to RA again ú ALU output is x 2 + 2x. § How do we make this happen?

Making the calculation High-level Steps Control Signals § SelxA = 0, ALUop = Pass, § Load X into RA & RB LdRA = 1, LdRB = 1 § SelxA = 1, SelAB = 1, § Multiply RA & RB ALUop = Multiply, LdRA = 1 ú Store result in RA § SelxA = 0, SelAB = 0, § Add X to RA ALUop = Add, LdRA = 1 ú Store result in RA § Add X to RA again § SelxA = 0, SelAB = 0, ú ALU output is x 2 + 2x. ALUop = Add § Who sends these signals?

Example schematic X LdRA LdRB RA RB 0 1 0 1 SelxA SelAB ALUop ALU