Processor Design Single Cycle Processor Hung-Wei Tseng Recap: the - - PowerPoint PPT Presentation

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Processor Design Single Cycle Processor Hung-Wei Tseng Recap: the - - PowerPoint PPT Presentation

May 21, 2023 27 likes •138 views

Processor Design Single Cycle Processor Hung-Wei Tseng Recap: the stored-program computer Store instructions in Processor memory The program counter PC instruction memory (PC) controls the 120007a30: 0f00bb27 ldah gp,15(t12)

slide-1
SLIDE 1

Processor Design － Single Cycle Processor

Hung-Wei Tseng

slide-2
SLIDE 2

Recap: the stored-program computer

  • Store instructions in

memory

  • The program counter

(PC) controls the execution

2

Processor PC

120007a30: 0f00bb27 ldah gp,15(t12) 120007a34: 509cbd23 lda gp,-25520(gp) 120007a38: 00005d24 ldah t1,0(gp) 120007a3c: 0000bd24 ldah t4,0(gp) 120007a40: 2ca422a0 ldl t0,-23508(t1) 120007a44: 130020e4 beq t0,120007a94 120007a48: 00003d24 ldah t0,0(gp) 120007a4c: 2ca4e2b3 stl zero,-23508(t1)

instruction memory

800bf9000: 00c2e800 12773376 800bf9004: 00000008 8 800bf9008: 00c2f000 12775424 800bf900c: 00000008 8 800bf9010: 00c2f800 12777472 800bf9014: 00000008 8 800bf9018: 00c30000 12779520 800bf901c: 00000008 8

data memory

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SLIDE 3

Recap: MIPS ISA

  • R-type: add, sub, and etc...
  • I-type: addi, lw, sw, beq, and etc...
  • J-type: j, jal, and etc...

3

  • pcode

rs rt rd

shift amount

funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

  • pcode

rs rt immediate / offset

6 bits 5 bits 5 bits 16 bits

  • pcode

target

6 bits 26 bits

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SLIDE 4

Outline

  • Implementing a MIPS processor
  • Single-cycle processor
  • Pipelined processor

4

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SLIDE 5

Designing a simple MIPS processor

  • Support MIPS ISA in hardware
  • Design the datapath: add and connect all the required elements

in the right order

  • Design the control path: control each datapath element to

function correctly.

  • Starts from designing a single cycle processor
  • Each instruction takes exactly one cycle to execute

5

slide-6
SLIDE 6

Basic steps of execution

  • Instruction fetch: fetch an

instruction from memory

  • Decode:
  • What’s the instruction?
  • Where are the operands?
  • Execute
  • Memory access
  • Where is my data? (The data

memory address)

  • Write back
  • Where to put the result
  • Determine the next PC

6

Processor PC

120007a30: 0f00bb27 ldah gp,15(t12) 120007a34: 509cbd23 lda gp,-25520(gp) 120007a38: 00005d24 ldah t1,0(gp) 120007a3c: 0000bd24 ldah t4,0(gp) 120007a40: 2ca422a0 ldl t0,-23508(t1) 120007a44: 130020e4 beq t0,120007a94 120007a48: 00003d24 ldah t0,0(gp) 120007a4c: 2ca4e2b3 stl zero,-23508(t1)

instruction memory data memory

800bf9000: 00c2e800 12773376 800bf9004: 00000008 8 800bf9008: 00c2f000 12775424 800bf900c: 00000008 8 800bf9010: 00c2f800 12777472 800bf9014: 00000008 8 800bf9018: 00c30000 12779520 800bf901c: 00000008 8

R0 R1 R2 R31

........

registers ALU

slide-7
SLIDE 7

Recap: MIPS ISA

  • R-type: add, sub, and etc...
  • I-type: addi, lw, sw, beq, and etc...
  • J-type: j, jal, and etc...

7

  • pcode

rs rt rd

shift amount

funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

  • pcode

rs rt immediate / offset

6 bits 5 bits 5 bits 16 bits

  • pcode

target

6 bits 26 bits

slide-8
SLIDE 8

Implementing an R-type instruction

10

  • pcode

rs rt rd shift amt funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

instruction = MEM[PC] REG[rd] = REG[rs] op REG[rt] PC = PC + 4

Read Address

Instruc(on Memory

PC ALU Write+Data 4 Add Read +Data+1 Read +Data+2 Read+Reg+1 Read+Reg+2 Write+Reg

Register File

inst[25:21] inst[20:16] inst[15:11] inst[31:0] ALUop

ALU control ALUop

Clock

Tell the ALU what ALU function to perform Tell the Processor when to start an instruction

slide-9
SLIDE 9

Implementing a load instruction

13

  • pcode

rs rt immediate / offset

6 bits 5 bits 5 bits 16 bits

instruction = MEM[PC] REG[rt] = MEM[signext(immediate) + REG[rs]] PC = PC + 4

Read Address

Instruc(on Memory

PC ALU Write+Data 4 Add Read +Data+1 Read +Data+2 Read+Reg+1 Read+Reg+2 Write+Reg

Register File

inst[25:21] inst[20:16] inst[15:11] inst[31:0]

m u x

1

m u x

1

sign- extend

32 16

Data Memory

Address Read Data

m u x

1

ALUop ALUSrc

MemtoReg

MemRead RegDst inst[31:26]

control

Set different control signals for different types

  • f instructions

Set to 0 if it’s a load Set to 1 if it’s a load Set to 1 if it’s a load

slide-10
SLIDE 10

Implementing a store instruction

16

  • pcode

rs rt immediate / offset

6 bits 5 bits 5 bits 16 bits

instruction = MEM[PC] MEM[signext(immediate) + REG[rs]] = REG[rt] PC = PC + 4

Read Address

Instruc(on Memory

PC ALU Write+Data 4 Add Read +Data+1 Read +Data+2 Read+Reg+1 Read+Reg+2 Write+Reg

Register File

inst[25:21] inst[20:16] inst[15:11] inst[31:0]

m u x

1

m u x

1

sign- extend

32 16

Data Memory

Address Read Data

m u x

1

Write+Data ALUSrc

MemtoReg

MemRead RegDst

RegWrite MemWrite

ALUop inst[31:26]

control

Set to 0 if it’s a store Set to 1 if it’s a store Set to 0 if it’s a store

slide-11
SLIDE 11

Implementing a branch instruction

18

  • pcode

rs rt immediate / offset

6 bits 5 bits 5 bits 16 bits

instruction = MEM[PC] PC = (REG[rs] == REG[rt]) ? PC + 4 + SignExtImmediate *4 : PC + 4

Read Address

Instruc(on Memory

PC ALU Write+Data 4 Add Read +Data+1 Read +Data+2 Read+Reg+1 Read+Reg+2 Write+Reg

Register File

inst[25:21] inst[20:16] inst[15:11] inst[31:0]

m u x

1

m u x

1

sign- extend

32 16

Data Memory

Address Read Data

m u x

1

Write+Data

m u x

1

Add Shi> le>?2 ALUSrc

MemtoReg

MemRead RegDst

RegWrite MemWrite PCSrc

Zero

PCSrc = Branch & Zero

ALUop inst[31:26]

control

Calculate the target address