multi cycle cpu
play

Multi Cycle CPU Jason Mars Monday, February 4, 13 Why a Multiple - PowerPoint PPT Presentation

Aug 23, 2022 •125 likes •1.07k views

Multi Cycle CPU Jason Mars Monday, February 4, 13 Why a Multiple Cycle CPU? Monday, February 4, 13 Why a Multiple Cycle CPU? The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine

  1. Multi Cycle CPU Jason Mars Monday, February 4, 13

  2. Why a Multiple Cycle CPU? Monday, February 4, 13

  3. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine Monday, February 4, 13

  4. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine • The solution => break up execution into smaller tasks, each task taking a cycle, di ff erent instructions requiring di ff erent numbers of cycles or tasks Monday, February 4, 13

  5. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine • The solution => break up execution into smaller tasks, each task taking a cycle, di ff erent instructions requiring di ff erent numbers of cycles or tasks • Other advantages => reuse of functional units (e.g., alu, memory) Monday, February 4, 13

  6. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine • The solution => break up execution into smaller tasks, each task taking a cycle, di ff erent instructions requiring di ff erent numbers of cycles or tasks • Other advantages => reuse of functional units (e.g., alu, memory) Monday, February 4, 13

  7. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine • The solution => break up execution into smaller tasks, each task taking a cycle, di ff erent instructions requiring di ff erent numbers of cycles or tasks • Other advantages => reuse of functional units (e.g., alu, memory) • ET = IC * CPI * CT Monday, February 4, 13

  8. High Level View Monday, February 4, 13

  9. Breaking Execution into Clock Cycles • We will have five execution steps (not all instructions use all five) • fetch • decode & register fetch • execute • memory access • write-back • We will use Register-Transfer-Language (RTL) to describe these steps Monday, February 4, 13

  10. Breaking Execution into Clock Cycles Monday, February 4, 13

  11. Breaking Execution into Clock Cycles • Introduces extra registers when: • Signal is computed in one clock cycle and used in another, AND • The inputs to the functional block that outputs this signal can change before the signal is written into a state element. Monday, February 4, 13

  12. Breaking Execution into Clock Cycles • Introduces extra registers when: • Signal is computed in one clock cycle and used in another, AND • The inputs to the functional block that outputs this signal can change before the signal is written into a state element. • Significantly complicates control. Why? Monday, February 4, 13

  13. Breaking Execution into Clock Cycles • Introduces extra registers when: • Signal is computed in one clock cycle and used in another, AND • The inputs to the functional block that outputs this signal can change before the signal is written into a state element. • Significantly complicates control. Why? • The goal is to balance the amount of work done each cycle. Monday, February 4, 13

  14. Multi-Cycle Datapath Monday, February 4, 13

  15. Multi-Cycle Datapath • More Latches Monday, February 4, 13

  16. Multi-Cycle Datapath • More Latches • One ALU Monday, February 4, 13

  17. Multi-Cycle Datapath • More Latches • One ALU • One Memory Unit Monday, February 4, 13

  18. 1. Fetch IR = Mem[PC] PC = PC + 4 ( may not be final value of PC ) Monday, February 4, 13

  19. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  20. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) • compute target before we know if it will be used (may not be branch, branch may not be taken ) Monday, February 4, 13

  21. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) • compute target before we know if it will be used (may not be branch, branch may not be taken ) • ALUOut is a new state element (temp register ) Monday, February 4, 13

  22. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) • compute target before we know if it will be used (may not be branch, branch may not be taken ) • ALUOut is a new state element (temp register ) • everything up to this point must be Instruction- independent, because we still haven’t decoded the instruction . Monday, February 4, 13

  23. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) • compute target before we know if it will be used (may not be branch, branch may not be taken ) • ALUOut is a new state element (temp register ) • everything up to this point must be Instruction- independent, because we still haven’t decoded the instruction . • everything instruction (opcode)-dependent from here on . Monday, February 4, 13

  24. 3. Execution, Memory Address Computation, or Branch Completion • Memory reference (load or store) • ALUOut = A + sign-extend(IR[15-0]) • R-type • ALUout = A op B • Branch • if (A == B) PC = ALUOut At this point, Branch is complete, and we start over; others require more cycles. Monday, February 4, 13

  25. 4. Memory access or R-type completion • Memory reference (load or store) • Load • MDR = Mem[ALUout] • Store • Mem[ALUout] = B • R-type • Reg[IR[15-11]] = ALUout R-type is complete, store is complete. Monday, February 4, 13

  26. 5. Memory Write-Back Reg[IR[20-16]] = MDR load is complete Monday, February 4, 13

  27. Summary of Execution Steps Step R-type Memory Branch Instruction Fetch IR = Mem[PC] PC = PC + 4 Instruction Decode/ A = Reg[IR[25-21]] register fetch B = Reg[IR[20-16]] ALUout = PC + (sign-extend(IR[15-0]) << 2) Execution, address ALUout = A op B ALUout = A + if (A==B) then computation, branch sign- PC=ALUout completion extend(IR[15-0]) Memory access or R- Reg[IR[15-11]] = memory-data = type completion ALUout Mem[ALUout] or Mem[ALUout]= B Write-back Reg[IR[20-16]] = memory-data Monday, February 4, 13

  28. Complete Multi-Cycle Datapath Monday, February 4, 13

  29. Complete Multi-Cycle Datapath New Instruction Appears Out of Nowhere? Which One? Monday, February 4, 13

  30. 1. Instruction Fetch IR = Memory[PC] PC = PC + 4 Monday, February 4, 13

  31. 1. Instruction Fetch IR = Memory[PC] PC = PC + 4 Monday, February 4, 13

  32. 1. Instruction Fetch IR = Memory[PC] PC = PC + 4 Monday, February 4, 13

  33. 1. Instruction Fetch IR = Memory[PC] PC = PC + 4 Monday, February 4, 13

  34. 2. Instruction Decode and Register Fetch A = Register[IR[25-21]] B = Register[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  35. 2. Instruction Decode and Register Fetch A = Register[IR[25-21]] B = Register[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  36. 2. Instruction Decode and Register Fetch A = Register[IR[25-21]] B = Register[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  37. 2. Instruction Decode and Register Fetch A = Register[IR[25-21]] B = Register[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  38. 3. Execution (R-Type) ALUout = A op B Monday, February 4, 13

  39. 3. Execution (R-Type) ALUout = A op B Monday, February 4, 13

  40. 4. R-Type Completion Reg[IR[15-11]] = ALUout Monday, February 4, 13

  41. 4. R-Type Completion Reg[IR[15-11]] = ALUout Monday, February 4, 13

  42. 4. R-Type Completion Reg[IR[15-11]] = ALUout Monday, February 4, 13

  43. 3. Branch Completion if (A == B) PC = ALUOut Monday, February 4, 13

  44. 3. Branch Completion if (A == B) PC = ALUOut Monday, February 4, 13

  45. 3. Branch Completion if (A == B) PC = ALUOut Monday, February 4, 13

  46. 4. Memory Address Computation ALUout = A + sign-extend(IR[15-0]) Monday, February 4, 13

  47. 4. Memory Address Computation ALUout = A + sign-extend(IR[15-0]) Monday, February 4, 13

  48. 4. Memory Address Computation ALUout = A + sign-extend(IR[15-0]) Monday, February 4, 13

  49. 4. Memory Access Load memory-data = Memory[ALUout] Monday, February 4, 13

  50. 4. Memory Access Load memory-data = Memory[ALUout] Monday, February 4, 13

  51. 4. Memory Access Load memory-data = Memory[ALUout] Monday, February 4, 13

  52. 4. Memory Access Store Memory[ALUout] = B Monday, February 4, 13

  53. 4. Memory Access Store Memory[ALUout] = B Monday, February 4, 13

  54. 4. Memory Access Store Memory[ALUout] = B Monday, February 4, 13

  55. 5. Load Write-Back Reg[IR[20-16]] = memory-data Monday, February 4, 13

  56. 5. Load Write-Back Reg[IR[20-16]] = memory-data Monday, February 4, 13

  57. 5. Load Write-Back Reg[IR[20-16]] = memory-data Monday, February 4, 13

  58. 3. Jump Completion PC = PC[31-28] | (IR[25-0] <<2) Monday, February 4, 13

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend

The Cycle The Cycle ULI Multi-Family Gold Council ULI Multi-Family Gold Council Wednesday,

The Cycle The Cycle ULI Multi-Family Gold Council ULI Multi-Family Gold Council Wednesday,

The Cycle The Cycle ULI Multi-Family Gold Council ULI Multi-Family Gold Council Wednesday, November 6, 2013 11:00 AM 11:45 AM Charles Hewlett, Managing Director, RCLCO AGENDA The Cycle where we are now, how do you Moderator: know

665 views • 29 slides
Multi-Cycle CPU: Datapath and Control CSE 141, S2'06 Jeff Brown Why a Multiple Clock Cycle CPU?

Multi-Cycle CPU: Datapath and Control CSE 141, S2'06 Jeff Brown Why a Multiple Clock Cycle CPU?

Multi-Cycle CPU: Datapath and Control CSE 141, S2'06 Jeff Brown Why a Multiple Clock Cycle CPU? the problem =&gt; single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine the solution =&gt; break

559 views • 38 slides
Unit 5: Pipelining Load-use stalling Pipelined multi-cycle operations Control hazards

Unit 5: Pipelining Load-use stalling Pipelined multi-cycle operations Control hazards

This Unit: Pipelining App App App Single-cycle &amp; multi-cycle datapaths System software Latency vs throughput &amp; performance Basic pipelining CIS 501: Computer Architecture Mem CPU I/O Data hazards Bypassing Unit

522 views • 24 slides
Lecture 16: Basic CPU Design Todays topics: Single-cycle CPU Multi-cycle CPU

Lecture 16: Basic CPU Design Todays topics: Single-cycle CPU Multi-cycle CPU

Lecture 16: Basic CPU Design Todays topics: Single-cycle CPU Multi-cycle CPU Reminder: Assignment 6 will be posted today due in a week 1 Basic MIPS Architecture Now that we understand clocks and storage of states,

349 views • 20 slides
Cycle 4c: R-type result write (add, and) Inf2C Computer Systems - 2013-2014 19 What happens in

Cycle 4c: R-type result write (add, and) Inf2C Computer Systems - 2013-2014 19 What happens in

Lecture 9: Processor design multi cycle Aren t single cycle processors good enough? No! Speed: cycle time must be long enough for the most complex instruction to complete But the average instruction needs less time Cost:

458 views • 22 slides
Lecture 9: Processor design multi cycle Arent single cycle processors good enough? No!

Lecture 9: Processor design multi cycle Arent single cycle processors good enough? No!

Lecture 9: Processor design multi cycle Arent single cycle processors good enough? No! Speed: cycle time must be long enough for the most complex instruction to complete But the average instruction needs less time Cost:

901 views • 12 slides
Red Shift Multi Core Effective Cycle Time 1995 1993 Memory Access Time 1991 CPU Cycle Time

Red Shift Multi Core Effective Cycle Time 1995 1993 Memory Access Time 1991 CPU Cycle Time

2007 2005 2003 2001 1999 1997 Red Shift Multi Core Effective Cycle Time 1995 1993 Memory Access Time 1991 CPU Cycle Time 1989 1987 1985 1984 1982 1000 1000 100 10 1 0.1 0.01 anoseconds na Because of Red Shift Todays

469 views • 25 slides
Architecture and Synthesis for Multi- -Cycle Cycle Architecture and Synthesis for Multi On-

Architecture and Synthesis for Multi- -Cycle Cycle Architecture and Synthesis for Multi On-

Architecture and Synthesis for Multi- -Cycle Cycle Architecture and Synthesis for Multi On- -Chip Communication Chip Communication On Jason Cong Jason Cong VLSI CAD Lab VLSI CAD Lab Computer Science Department Computer Science

898 views • 41 slides
Outline Combinational &amp; sequential logic Single-cycle CPU Multi-cycle CPU 1

Outline Combinational &amp; sequential logic Single-cycle CPU Multi-cycle CPU 1

Outline Combinational &amp; sequential logic Single-cycle CPU Multi-cycle CPU 1 Combinational Element combinational n n input output logic Output determined entirely by input Contains no storage element 2 Examples of

1.15k views • 94 slides
Pure-cycle Hurwitz factorizations and multi-noded rooted trees by Rosena Ruoxia Du East China

Pure-cycle Hurwitz factorizations and multi-noded rooted trees by Rosena Ruoxia Du East China

Pure-cycle Hurwitz factorizations and multi-noded rooted trees Rosena R.X. Du Pure-cycle Hurwitz factorizations and multi-noded rooted trees by Rosena Ruoxia Du East China Normal University Combinatorics Seminar, SJTU August 29, 2013 This is

733 views • 44 slides
Application of the next generation of the OSCAR code system to the ETRR-2 multi-cycle depletion

Application of the next generation of the OSCAR code system to the ETRR-2 multi-cycle depletion

Application of the next generation of the OSCAR code system to the ETRR-2 multi-cycle depletion benchmark M. Mashau, S.A. Groenewald, F.A. van Heerden The South African Nuclear Energy Corporation (Necsa) SOC Ltd, Building P1900, P.O. Box 582,

520 views • 24 slides
CO2101 Processes and Multi-tasking Tom Ridge (tr61) 7th October 2019 tr61 Multi-tasking

CO2101 Processes and Multi-tasking Tom Ridge (tr61) 7th October 2019 tr61 Multi-tasking

CO2101 Processes and Multi-tasking Tom Ridge (tr61) 7th October 2019 tr61 Multi-tasking 7th October 2019 1 / 33 How to implement multi-tasking Why multi-tasking? Simple Fetch-Execute Cycle CPU operates in a Fetch-Execute cycle it

1.27k views • 108 slides
Based on MIPS In fact, its based on the multi-cycle MIPS from Patterson and Hennessy

Based on MIPS In fact, its based on the multi-cycle MIPS from Patterson and Hennessy

Mini-MIPS From Weste/Harris CMOS VLSI Design Based on MIPS In fact, its based on the multi-cycle MIPS from Patterson and Hennessy Your CS/EE 3810 book... 8-bit version 8-bit data and address 32-bit instruction format 8

614 views • 27 slides
Multi-Dimensional Spatially-Coupled Code Design with Improved Cycle Properties Homa

Multi-Dimensional Spatially-Coupled Code Design with Improved Cycle Properties Homa

Multi-Dimensional Spatially-Coupled Code Design with Improved Cycle Properties Homa Esfahanizadeh, Dr. Ahmed Hareedy, and Prof. Lara Dolecek ECE Department, UCLA 03/11/2019 Presentation Outline w Motivation w Preliminaries LDPC Codes and

1.1k views • 55 slides
Precise Exceptions and Out-of-Order Execution Samira Khan Multi-Cycle Execution Not all

Precise Exceptions and Out-of-Order Execution Samira Khan Multi-Cycle Execution Not all

Precise Exceptions and Out-of-Order Execution Samira Khan Multi-Cycle Execution Not all instructions take the same amount of time for execution Idea: Have multiple different functional units that take different number of cycles

749 views • 39 slides
Accelerate Cycle-Level Multi-Core RISC-V Simulation with Binary Translation Xuan Guo, Robert

Accelerate Cycle-Level Multi-Core RISC-V Simulation with Binary Translation Xuan Guo, Robert

Accelerate Cycle-Level Multi-Core RISC-V Simulation with Binary Translation Xuan Guo, Robert Mullins Department of Computer Science and Technology Both the paper and the slides are made available under CC BY 4.0 Motivation We want to

790 views • 22 slides
COMP 110-003 Introduction to Programming Computer Basics January 10, 2013 Haohan Li TR 11:00

COMP 110-003 Introduction to Programming Computer Basics January 10, 2013 Haohan Li TR 11:00

COMP 110-003 Introduction to Programming Computer Basics January 10, 2013 Haohan Li TR 11:00 12:15, SN 011 Spring 2013 Today Hardware and Memory Programs and Compiling Your first program Before Programming You need to

310 views • 17 slides
61A Lecture 26 Announcements Programming Languages Programming Languages 4 Programming

61A Lecture 26 Announcements Programming Languages Programming Languages 4 Programming

61A Lecture 26 Announcements Programming Languages Programming Languages 4 Programming Languages A computer typically executes programs written in many different programming languages 4 Programming Languages A computer typically executes

1.66k views • 151 slides
Android Smartphone as a Microphone in SmartRoom System Pavel Y. Kovyrshin, Dmitry G. Korzun

Android Smartphone as a Microphone in SmartRoom System Pavel Y. Kovyrshin, Dmitry G. Korzun

Android Smartphone as a Microphone in SmartRoom System Pavel Y. Kovyrshin, Dmitry G. Korzun Petrozavodsk State University Department of Computer Science Grant KA179 Complex development of regional cooperation in the field of open ICT

576 views • 11 slides
The Energy/Frequency Convexity Rule of Energy Consumption for Programs: Modeling,

The Energy/Frequency Convexity Rule of Energy Consumption for Programs: Modeling,

The Energy/Frequency Convexity Rule of Energy Consumption for Programs: Modeling, Thermosensitivity, and Applications Karel De Vogeleer Ph.D. defense September 4th, 2015 Special thanks to Fondation TELECOM for funding this research

849 views • 39 slides
Practicing Law with Humility (Part Deux) How can Indigenous Laws make Canadian Lawyers better?

Practicing Law with Humility (Part Deux) How can Indigenous Laws make Canadian Lawyers better?

Practicing Law with Humility (Part Deux) How can Indigenous Laws make Canadian Lawyers better? Amanda Carling Manager, Indigenous Initiatives 1L Ethics Training January 31, 2020 Warm up are you paying attention? Humility in the

578 views • 34 slides
A sound curation in musical instrument conservation Gea O.F . Parikesit, Nicole A. Tse, Rong Wei

A sound curation in musical instrument conservation Gea O.F . Parikesit, Nicole A. Tse, Rong Wei

A sound curation in musical instrument conservation Gea O.F . Parikesit, Nicole A. Tse, Rong Wei Sim, Margaret Kartomi, Robyn Sloggett Universitas Gadjah Mada, University of Melbourne, Monash University 14th International Digital Curation

812 views • 25 slides
C oprocessor A ccelerated F ilterbank Extension Library Mummy, are we there yet Jan Kr amer

C oprocessor A ccelerated F ilterbank Extension Library Mummy, are we there yet Jan Kr amer

C oprocessor A ccelerated F ilterbank Extension Library Mummy, are we there yet Jan Kr amer DLR Institute of Communication and Navigation (IKN) 04.02.2018 Overview Introduction Arbitrary Resampler Transition to the GPU Open Sourcing Jan

631 views • 25 slides
FUTURE INTERNET Testbed @TWAREN Che-Nan Yang NCHC,Taiwan Overview OpenFlow Testbed in

FUTURE INTERNET Testbed @TWAREN Che-Nan Yang NCHC,Taiwan Overview OpenFlow Testbed in

FUTURE INTERNET Testbed @TWAREN Che-Nan Yang NCHC,Taiwan Overview OpenFlow Testbed in TWAREN HPDMnet Multicast Streaming with OpenFlow Future Work 2 Future Internet There are many serious limitations in current Internet.

505 views • 28 slides

More recommend