[PPT] - CISC Design Hardware Flowchart Virendra Singh Associate Professor PowerPoint Presentation

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CISC Design

Hardware Flowchart

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

EE-739: Processor Design

Lecture 5

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Micro-coded Implementation

Clock-Phase Generator Bus Controller

Control Word Decoder

PC R0 R1 Rn Shifter ALU

Datapath

Data Reg. Address Out Reg. Internal A Bus Internal B Bus

Control Store Instruction Sequencer Instruction Decoder

Instruction Prefetch Register Encoded Control Word Fields

Decoded Datapath Control

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Instruction Execution

 The second operand is added in the first  The sum is placed in the first operand location  The operand and the sum are treated as 16-bit signed binary integers  The first operand is in the register specified by the R1 field  The second operand is in the memory – address is calculated by adding the displacement specified by the D2 field to the content of the base register specified by the B2 field

‘5A’ R1 B2 D2

8 12 16 31

ADD R1, D2(B2)

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Execution Steps

Steps for ADD instruction Execution

1. Fetch the first half word
2. Find ADD control word sequence
3. Fetch the remaining instruction word
4. Calculate the operand address
5. Fetch the operand
6. Add
7. Store the result

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Execution Steps

1. Fetch the remaining instruction word
2. Calculate the operand address
3. Fetch the operand
4. Add
5. Store the result
6. Update the program counter
7. Fetch the first half word for the next instruction
8. Find the address of the next instructions control word

sequence

9. Branch to the next instruction’s control word

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Execution Steps

1. Fetch the remaining instruction word
One state to second half of the ADD instruction
2. Calculate the operand address
One state to add D2 displacement and the content of the B2

register

3. Fetch the operand
One state to fetch the data half word (put the address on the

pads and wait for the operand half-word)

4. Add
One state to add the operands
5. Store the result
One state to store the result in Register R1

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Execution Steps

6. Update the program counter
One state to increament PC
One state to save the incremented value
6. Fetch the first half word for the next instruction
One state to put the PC value on the pads and wait for the

first half of the next instruction

6. Find the address of the next instructions control word

sequence

One state to put the next instruction into the instruction

decoder

6. Branch to the next instruction’s control word
Zero state – this step is accomplished as a part of the

previous step

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Processor - Block Diagram

Clock-Phase Generator

Control Word Decoder

PC R0 R1 Rn Shifter ALU

Datapath

Data Reg. Address Out Reg. Internal A Bus Internal B Bus

Control Store

Next State Control

IR Decoder

Instruction Prefetch Register Encoded Control Word Fields

Decoded Datapath Control

Branch Control unit

Reset & Power-On Logic Interrupt Logic Bus Controller

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Hardware Flowchart

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Hardware Flowchart

Pre-requisites:  Instruction set summary

Instruction Format
Operations
Addressing modes
Registers

 Datapath

Programmer’s

register set

Additional

registers

ALU and any

special functional units

Internal data

paths

Datapath will evolve

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Development of Implementation

Clock Phase Generator Datapath

The architecture

specification is the

nly input
Begin with a guess
f Datapath
Do flowchart for the

instructions

This modifies and

refines the Datapath and develops the control store and control strategy

The final Datapath is

derived output

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Development of Implementation

Clock Phase Generator Datapath

Control Store

Control Word

Once flowcharts

are fairly complete, derive the control word format using the flowchart states

When the

flowcharts are complete, so is the Datapath

Control word

format is derived

utput

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Development of Implementation

Clock Phase Generator Datapath

Control Store

Control Word Decoder

After defining

control word format, you assign bit patterns to the control fields in a way that minimizes control word decoders between the control store and the Datapath

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Development of Implementation

Clock Phase Generator Datapath

Control Store

Control Word Decoder Instruction Decoder

Instruction

decoders are defined the flowcharts and the architecture specification

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Development of Implementation

Clock Phase Generator Datapath

Control Store

Control Word Decoder Instruction Decoder Bus Controller

Completed

flowchars, control word format, and the initial bus specification defines the bus controller

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Development of Implementation

Clock Phase Generator Datapath

Control Store

Control Word Decoder Instruction Decoder Bus Controller State Sequencer

Last is the logic of

the state sequencer, the part

f the chip that

says what to do next (where is the next control word?)

Once every thing

around it is defined, you build exactly what you need! (The state sequencer is derived output)

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Flowchart Objective

Limit controller size to some fraction of

chip area

Make CPU as fast as possible
Complete the project as early as

possible

Make the flowcharts easy to translate

into hardware

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Example: MIN Instruction Set

Instruction Format

Displacement Op-code Rx Mode Ry

Operation Code First Operand Register Second Operand Address Mode First Operand Register

First Word Second Word

Optional, depending on second operand address mode R0 R1 R2 Rn . . . Programmer’s Register Set

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MIN Instruction Set

 ADD  AND  BZ – Branch if zero bit is set. (Register Indirect

nly)

 LOAD – Second operand is source and Rx is

destination

 POP – Postincrement with register indirect only  PUSH – Predecrement with register indirect only  STORE  SUB  TEST

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MIN Instruction Set

Second Operand Address

Mode Ry

Second Operand Address Mode First Operand Register

Address Modes

AB - Base (Ry) plus displacement (second

instruction word) is an operand address

AI – Register indirect. Ry holds an operand address
AR – Register direct: The result is stored in Ry. For

two operand instructions, Ry also is an operand source

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MIN Datapath

AO PC T2 R0 R1 Rn T1 ALU DO DI IRF IRE k

Internal A Bus Internal B Bus External Address Bus (EAB) External Data Bus (EDB)

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MIN Datapath

Rules of Operation

1. A transfer from source to bus to destination takes one

state time

2. A source can drive up to three destination loads
3. Inputs to the ALU are from A (internal) bus and either k

(values 0, +1, -1) or the B (internal) bus

4. When ALU is destination. T1 is automatically loaded

from the ALU output

5. A transfer to AO activates the on-chip external bus
controller. This bus controller postpones the next state

until the external transfer is complete.

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Flowcharts

Rx  a  alu Ry  b  alu T1  b  ry Edb  di Ry  b  ao Di  b  alu Rx  a  alu Ry  b  ao T1  a  do R  R ADD ADD R  M

ADD RX AR RY

Register-to-Register

ADD RX AI (RY)

Register-to-Memory

State Sequence

AO PC T2 R0 R1 Rn T1 ALU DO DI IRF IRE k Internal A Bus Internal B Bus