Embedded systems & the Nios II soft core processor A Nios II - - PowerPoint PPT Presentation

embedded systems the nios ii soft core processor a nios
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Embedded systems & the Nios II soft core processor A Nios II - - PowerPoint PPT Presentation

Embedded systems & the Nios II soft core processor A Nios II processor system I equivalent to a microcontroller or System on a chip (SoC) The Nios II processor family consits of two configurable 32-bit Harvard architecture cores Fast (/f


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SLIDE 1

Embedded systems & the Nios II soft core processor

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SLIDE 2

A Nios II processor system I equivalent to a microcontroller or System on a chip (SoC)

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SLIDE 3

The Nios II processor family consits of two configurable 32-bit Harvard architecture cores

Fast (/f core): Six-stage pipeline optimized for highest performance, optional memory management unit, or memory protection unit Economy (/e core): Optimized for smallest size, and available at no cost (no license required)

  • One-stage pipeline à one instruction

per six clock cycles

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SLIDE 4

Choosing the core in Platform Designer

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SLIDE 5

NIOS–II Core block diagram

  • A general-purpose RISC

processor core

  • 32-bit instruction set, data

path, and address space

  • 32 general-purpose registers
  • Optional shadow register sets –

useful for context switching on multitasking systems (e.g. Interrupts, RTOS)

  • 32 interrupt sources
  • External interrupt controller

interface for more interrupt sources

  • Supports single-precision

floating-point operations

Nios II Processor Reference Guide, Intel, Available online: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf

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SLIDE 6

Nios II performance

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures

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SLIDE 7

Nios II performance

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures

ARM Cortex – M1 ARM Cortex - A9 Compared to:

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SLIDE 8

Nios II performance

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SLIDE 9

Example minimum implementation

MAX 10 in chip planner

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SLIDE 10

NIOS II

  • A widely used soft processors in the

FPGA industry

– Soft core IP

  • Supports Intel’s (former Altera)

FPGAs and is even available for standard-cell ASICs (Synopsys).

  • Access to a variety of on-chip

peripherals and interfaces to off-chip memories and peripherals

  • Software development environment

based on the GNU C/C++ tool chain and Eclipse IDE.