Lecture 16: Midterm Review (RTL and Timing) CSE 140: Components and - PowerPoint PPT Presentation

Lecture 16: Midterm Review (RTL and Timing) CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1

Final breakup • Multiple Choice (Misc): 12% • Timing and MUX/Decoder: 38% • RTL Design and Simulating circuit behavior in RTL: 50%

RTL Design (HLSM) • Deriving the HLSM (simple examples) • Simulating the circuit behavior (via timing diagrams)

Problem: Input B (1 bit), output P(1 bit) should go high for two clock cycles every time B goes high

HLSMs Q: What is the final state that is Local storage : R, Q (8 bits) reached for the given HLSM? C R<100 A B (R<100)' A. State A R:=99 R:=R+1 D B. State B Q:=R C. State C D. State D 7

HLSMs Q: What is the final state that is Local storage : R, Q (8 bits) reached for the given HLSM? C R<100 A B (R<100)' A. State A R:=99 R:=R+1 D B. State B Q:=R C. State C R<100 D. State D A B clk 99 100 R ? 99 100 Q ? ? ? 8

HLSMs Q: Are the two HLSMs equivalent? Local storage : R, Q (8 bits) HLSM 1 C R<100 A. Yes A B (R<100)' B. No R:=99 R:=R+1 D Q:=R Local storage : R, Q (8 bits) C HLSM 2 R<100 A B (R<100)' R:=R+1 D Q:=R R:=99 9

Function Modules: Counter (updates to i) operation A ß ß Load (X) B ß ß Load (Y) B ß SHL(B) A Selector Register A Register M M ß ß Clear(M) Adder S M ß Add(M,A) 0 B R A X D R D M ß SHL(M) M 16 16 LD i ß Clear(i) LD CLR 1 i ß INC(i) << C 0 C 2 C 4 C 1 SHL Selector Register B 16 Y 0 B B[15] R Counter i D << D R LD 1 SHL CLR Inc i[4] C 3 C 5 C 6 C 7 10 Source: CK Cheng

Step 2d: Map Control Signals to Operations operation A ß ß Load (X) C 0 =1 B ß ß Load (Y) C 5 =0 and C 3 =1 A Selector B ß SHL(B) C 5 =1 and C 3 =1 Register A Register M Adder M ß ß Clear(M) C 2 =1 S 0 B M ß Add(M,A) C 4 =0 and C 1 =1 R A X D R D M M ß SHL(M) C 4 =1 and C 1 =1 16 16 LD LD CLR 1 i ß Clear(i) C 6 =1 i ß INC(i) C 7 =1 << C 0 C 2 C 4 C 1 SHL Selector Register B 16 Y 0 B B[15] R Counter i D << D R LD 1 SHL CLR Inc i[4] C 3 C 5 C 6 C 7 11 Source: CK Cheng

16 32 X Data 16 Z Y Subsystem B[15], i[4] C 0:7 Control start Subsystem done 12 Source: CK Cheng

Design the Control Subsystem Multiply(X, Y, Z, start, done) operation { A ß ß Load (X) C 0 =1 S0: If start’ goto S0 || done ß ß 1; B ß ß Load (Y) C 5 =0 and C 3 =1 S1: A ß ß X || B ß ß Y || i ß ß 0 || M ß ß 0 || done ß ß 0; B ß SHL(B) C 5 =1 and C 3 =1 S2: If B 15 = 0 goto S4 || i ß ß i+1; M ß ß Clear(M) C 2 =1 S3: M ß ß M+A; M ß Add(M,A) C 4 =0 and C 1 =1 S4: if i>= 16, goto S6 M ß SHL(M) C 4 =1 and C 1 =1 S5: M ß ß Shift(M,L,1) || B ß ß Shift(B,L,1) || goto S2; i ß Clear(i) C 6 =1 S6: Z: ß ß M || done ß ß 1|| goto S0 i ß INC(i) C 7 =1 } Multiply(X, Y, Z, start, done) { S0: If start’ goto S0 || done ß ß 1; S1: C 0 =1 || C 5 =0 and C 3 =1 || C 6 =1|| C 2 =1 || done ß ß 0; S2: If B 15 = 0 goto S4 || C 7 =1; S3: C 4 =0 and C 1 =1; S4: if i[4], goto S6 S5: C 4 =1 and C 1 =1|| C 5 =1 and C 3 =1 || goto S2; S6: Z: ß ß M || done ß ß 1|| goto S0 } 13 Source: CK Cheng

Control Subsystem S6 S0 start’ start Multiply(X, Y, Z, start, done) { S1 S5 S0: If start’ goto S0 || done ß ß 1; S1: C 0 =1 || C 5 =0 and C 3 =1 || C 6 =1|| C 2 =1 || done ß ß 0; S2: If B 15 = 0 goto S4 || C 7 =1; S3: C 4 =0 and C 1 =1; S2 i[4] S4: if i[4], goto S6 i[4]’ S5: C 4 =1 and C 1 =1|| C 5 =1 and C 3 =1 || goto S2; B[15] ’ B[15] S6: Z: ß ß M || done ß ß 1|| goto S0 } S3 S4 14 Source: CK Cheng

One-Hot State Machine S6 S0 start’ start S1 S5 i[4] S2 i[4]’ B[15] ’ B[15] S3 S4 15 Source: CK Cheng

One-Hot State Machine S0 start’ start S6 S0 start’ start S1 S1 S5 S6 S2 S2 i[4] i[4]’ B[15] ’ B15’ B15 B[15] i[4] S3 S4 S5 S4 S3 i[4]’ 16 Source: CK Cheng

Control Subsystem: One-Hot State Machine Design Input: State Diagram 1. Use a flip flop to replace each state. 2. Set the flip flop which corresponds to the initial state and reset the rest flip flops. 3. Use an OR gate to collect all inward edges. 4. Use a Demux to distribute the outward edges. 17 Source: CK Cheng

Data Subsystem A Selector Register A Register M Adder S 0 B R A X D R D M 16 16 LD LD CLR 1 << C 0 C 2 C 4 C 1 SHL Selector Register B 16 Y 0 B B[15] R Counter i D << D R LD 1 SHL CLR Inc i[4] C 3 C 5 C 6 C 7 18 Source: CK Cheng

Multiply(X, Y, Z, start, done) { S0: If start’ goto S0 || done ß ß 1; S1: C 0 =1 || C 5 =0 and C 3 =1 || C 6 =1|| C 2 =1 || done ß ß 0; S2: If B 15 = 0 goto S4 || C 7 =1; S3: C 4 =0 and C 1 =1; S4: if i[4], goto S6 S5: C 4 =1 and C 1 =1|| C 5 =1 and C 3 =1 || goto S2; S6: Z: ß ß M || done ß ß 1|| goto S0 } C0 C1 C2 C3 C4 C5 C6 C7 done (mux) (mux) S0 0 0 0 0 X X 0 0 1 S1 1 0 1 0 X 0 1 0 0 S2 0 0 0 1 X X 0 1 0 S3 0 1 0 0 0 X 0 0 0 S4 0 0 0 0 X X 0 0 0 S5 0 1 0 1 1 1 0 0 0 S6 0 0 0 0 X X 0 0 1 19 Source: CK Cheng

Best of luck for the Final Exam! 20