SLIDE 1
Overview
¨ Announcement
¤ Homework 3 submission deadline: Nov. 11th
¨ This and the following lectures
¤ Dynamic random access memory (DRAM) ¤ DRAM operations ¤ Memory scheduling basics ¤ Emerging memory technologies
MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School - - PowerPoint PPT Presentation
MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School - - PowerPoint PPT Presentation
MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture Overview Announcement Homework 3 submission deadline: Nov. 11 th This and the following lectures
SLIDE 2
SLIDE 3
Computer System Overview
¨ DRAM technology is commonly used for main
memory
SLIDE 4
Computer System Overview
¨ DRAM technology is commonly used for main
memory
CPU
SLIDE 5
Computer System Overview
¨ DRAM technology is commonly used for main
memory
CPU Memory
SLIDE 6
Computer System Overview
¨ DRAM technology is commonly used for main
memory
CPU Memory
¨ SRAM is used for
caches
¨ DRAM is used for
main memory
¨ DRAM is accessed
- n a TLB or last
level cache miss
SLIDE 7
Static vs. Dynamic RAM
¨ Fast and leaky
¤ 6 transistors per bit ¤ Normal CMOS Tech.
¨ Static volatile
¤ Retain data as long as
powered on
¨ Dense and slow
¤ 1 transistor per bit ¤ Special DRAM process
¨ Dynamic volatile
¤ Periodic refreshing is
required to retain data
Static RAM (SRAM) Dynamic RAM (DRAM)
SLIDE 8
DRAM Organization
¨ DRAM array is organized as rows×columns
SLIDE 9
DRAM Organization
¨ DRAM array is organized as rows×columns
wordline bitline
SLIDE 10
DRAM Organization
¨ DRAM array is organized as rows×columns
decoder
wordline bitline
SLIDE 11
DRAM Organization
¨ DRAM array is organized as rows×columns
decoder Sense Amplifier row buffer
wordline bitline
SLIDE 12
DRAM Organization
¨ DRAM array is organized as rows×columns
decoder Sense Amplifier row buffer
wordline bitline
Data Block multiplexer
SLIDE 13
DRAM Organization
¨ DRAM array is organized as rows×columns
decoder Row Address Column Address Sense Amplifier row buffer
wordline bitline
Data Block multiplexer
SLIDE 14
DRAM Organization
¨ DRAM array is organized as rows×columns
decoder Row Address Column Address Sense Amplifier row buffer
wordline bitline
Data Block multiplexer All reads and writes are performed through the row buffer
SLIDE 15
Reading DRAM Cell
¨ DRAM read is destructive
¤ After a read, contents of cells are destroyed
Precharge Activate Sense Reading a zero Reading a one
SLIDE 16
Reading DRAM Cell
¨ DRAM read is destructive
¤ After a read, contents of cells are destroyed
Precharge Activate Sense Reading a zero Reading a one
V/2 ?
SLIDE 17
Reading DRAM Cell
¨ DRAM read is destructive
¤ After a read, contents of cells are destroyed
Precharge Activate Sense Reading a zero Reading a one
V/2 ? 1 V/2 ?
SLIDE 18
Reading DRAM Cell
¨ DRAM read is destructive
¤ After a read, contents of cells are destroyed
Precharge Activate Sense Reading a zero Reading a one
V/2 ? 1 V/2 ? 1 V/2 + ℇ
SLIDE 19
Reading DRAM Cell
¨ DRAM read is destructive
¤ After a read, contents of cells are destroyed
Precharge Activate Sense Reading a zero Reading a one
V/2 ? 1 V/2 ? 1 V/2 + ℇ V/2 ?
SLIDE 20
Reading DRAM Cell
¨ DRAM read is destructive
¤ After a read, contents of cells are destroyed
Precharge Activate Sense Reading a zero Reading a one
V/2 ? 1 V/2 ? 1 V/2 + ℇ V/2 ? 1 V/2 ?
SLIDE 21
Reading DRAM Cell
¨ DRAM read is destructive
¤ After a read, contents of cells are destroyed
Precharge Activate Sense Reading a zero Reading a one
V/2 ? 1 V/2 ? 1 V/2 + ℇ V/2 ? 1 V/2 ? 1 V/2 - ℇ V
SLIDE 22
DRAM Row Buffer
¨ All reads and writes are performed through RB
Data Array Row Buffer (RB) DRAM Cell DRAM Sense Amp. Row Access Strobe (RAS) Column Access Strobe (CAS)
SLIDE 23
DRAM Row Buffer
¨ Row buffer holds a single row of the array
¤ A typical DRAM row (page) size is 8KB
¨ The entire row is moved to row buffer; but only a
block is accessed each time
¨ Row buffer access possibilities
¤ Row buffer hit: no need for a precharge or activate
n ~20ns only for moving data between pins and RB
¤ Row buffer miss: activate (and precharge) are needed
n ~40ns for an empty row n ~60ns for on a row conflict
SLIDE 24
DRAM Refresh
¨ Charge based memory cells may gradually lose
their states due to current leakage
¨ DRAM requires the cells’ contents to be read and
written periodically
¤ Burst refresh: refresh all of the cells each time
n Simple control mechanism
¤ Distributed refresh: a group of cells are refreshed
n Avoid blocking memory for a long time
n time bursts m time distributed