MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School - PowerPoint PPT Presentation

MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture

Overview ¨ Announcement ¤ Homework 3 submission deadline: Nov. 11 th ¨ This and the following lectures ¤ Dynamic random access memory (DRAM) ¤ DRAM operations ¤ Memory scheduling basics ¤ Emerging memory technologies

Computer System Overview ¨ DRAM technology is commonly used for main memory

Computer System Overview ¨ DRAM technology is commonly used for main memory CPU

Computer System Overview ¨ DRAM technology is commonly used for main memory CPU Memory

Computer System Overview ¨ DRAM technology is commonly used for main memory CPU ¨ SRAM is used for caches ¨ DRAM is used for main memory ¨ DRAM is accessed Memory on a TLB or last level cache miss

Static vs. Dynamic RAM Static RAM (SRAM) Dynamic RAM (DRAM) ¨ Fast and leaky ¨ Dense and slow ¤ 6 transistors per bit ¤ 1 transistor per bit ¤ Normal CMOS Tech. ¤ Special DRAM process ¨ Static volatile ¨ Dynamic volatile ¤ Retain data as long as ¤ Periodic refreshing is powered on required to retain data

DRAM Organization ¨ DRAM array is organized as rows × columns

DRAM Organization ¨ DRAM array is organized as rows × columns bitline wordline

DRAM Organization ¨ DRAM array is organized as rows × columns bitline wordline decoder

DRAM Organization ¨ DRAM array is organized as rows × columns bitline wordline decoder Sense Amplifier row buffer

DRAM Organization ¨ DRAM array is organized as rows × columns bitline wordline decoder Sense Amplifier row buffer multiplexer Data Block

DRAM Organization ¨ DRAM array is organized as rows × columns bitline wordline Row Address decoder Sense Amplifier row buffer multiplexer Column Address Data Block

DRAM Organization ¨ DRAM array is organized as rows × columns bitline wordline Row Address decoder Sense Amplifier row buffer multiplexer All reads and writes are Column performed through the row Address buffer Data Block

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense Reading a zero Reading a one

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 0 Reading a zero ? Reading a one

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 0 1 Reading a zero ? ? Reading a one

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + ℇ 0 1 1 Reading a zero ? ? 0 Reading a one

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + ℇ 0 1 1 Reading a zero ? ? 0 V/2 0 Reading a one ?

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + ℇ 0 1 1 Reading a zero ? ? 0 V/2 V/2 0 1 Reading a one ? ?

Reading DRAM Cell ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + ℇ 0 1 1 Reading a zero ? ? 0 V/2 V/2 V/2 - ℇ 1 0 1 Reading a one V ? ?

DRAM Row Buffer ¨ All reads and writes are performed through RB DRAM Cell Row Access Data Array Strobe (RAS) Column Access Row Buffer (RB) Strobe DRAM (CAS) Sense Amp.

DRAM Row Buffer ¨ Row buffer holds a single row of the array ¤ A typical DRAM row (page) size is 8KB ¨ The entire row is moved to row buffer; but only a block is accessed each time ¨ Row buffer access possibilities ¤ Row buffer hit: no need for a precharge or activate n ~20ns only for moving data between pins and RB ¤ Row buffer miss: activate (and precharge) are needed n ~40ns for an empty row n ~60ns for on a row conflict

DRAM Refresh ¨ Charge based memory cells may gradually lose their states due to current leakage ¨ DRAM requires the cells’ contents to be read and written periodically ¤ Burst refresh: refresh all of the cells each time n Simple control mechanism ¤ Distributed refresh: a group of cells are refreshed n Avoid blocking memory for a long time bursts distributed m n time time